[PATCH v6 4/4] phy: ti-pipe3: Fix clock leak in init error path

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Undocumented code and behavior change in SATA DPLL lock check
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commit f36ec24b5d21c1b1acd7d71c309954221f9b2ccb
Author: Hongling Zeng <zenghongling at kylinos.cn>

phy: ti-pipe3: Fix clock leak in init error path
    
When regmap_update_bits() fails in ti_pipe3_init() for PCIe mode,
the function returns the error without calling ti_pipe3_disable_clocks().
This patch adds proper clock cleanup in the PCIe error path.
    
Closes: https://lore.kernel.org/all/20260518023657.41852C2BCB0@smtp.kernel.org/

> diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c
> --- a/drivers/phy/ti/phy-ti-pipe3.c
> +++ b/drivers/phy/ti/phy-ti-pipe3.c

[ ... ]

> @@ -531,8 +533,9 @@ static int ti_pipe3_init(struct phy *x)
>  
>  	/* SATA has issues if re-programmed when locked */
>  	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
> -	if ((val & PLL_LOCK) && phy->mode == PIPE3_MODE_SATA)
> -		return ret;
> +	if ((val & PLL_LOCK) && phy->mode == PIPE3_MODE_SATA) {
> +		return 0;
> +	}

[Severity: Medium]
The commit message mentions adding clock cleanup for the PCIe error path,
but this modifies the SATA DPLL lock check to return 0 instead of ret.

Right above this block, ret can be assigned an error value when
bringing the DPLL out of IDLE:

	if (val & PLL_IDLE) {
		val &= ~PLL_IDLE;
		ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
		ret = ti_pipe3_dpll_wait_lock(phy);
	}

If ti_pipe3_dpll_wait_lock() fails and returns -EBUSY, but the subsequent
read of PLL_STATUS shows PLL_LOCK is set, does this change unintentionally
mask the error by returning 0?

Could the commit message be updated to describe this if the behavior change
was intentional?

>  
>  	/* Program the DPLL */
>  	ret = ti_pipe3_dpll_program(phy);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260619030214.1779043-1-zenghongling@kylinos.cn?part=4