[PATCH v5 phy-next 04/16] phy: lynx-28g: move data structures to core

[Ioana Ciornei]

On Wed, Jun 10, 2026 at 06:19:40PM +0300, Vladimir Oltean wrote:
> The goal is to avoid duplicating the core data structures when
> introducing the new lynx-10g driver.
> 
> We move the following to phy-fsl-lynx-core:
> - struct lynx_28g_pll -> struct lynx_pll. This has some
>   hardware-specific register fields which need to become hardware
>   agnostic (the PLL register layout is different for Lynx 10G), So:
>   - PLLnRSTCTL_DIS(pll->rstctl) becomes !pll->enabled
>   - PLLnRSTCTL_LOCK(pll->rstctl) becomes pll->locked
>   - FIELD_GET(PLLnCR1_FRATE_SEL, pll->cr1) becomes pll->frate_sel
>   - FIELD_GET(PLLnCR0_REFCLK_SEL, pll->cr0) becomes pll->refclk_sel
> - struct lynx_28g_lane -> struct lynx_lane
> - struct lynx_28g_priv -> struct lynx_priv
>   - field lane[LYNX_28G_NUM_LANE] has to be dynamically allocated. Not
>     all Lynx 10G SerDes blocks have 8 lanes.
> - LYNX_28G_NUM_PLL -> LYNX_NUM_PLL. This is an architectural constant
>   which is the same for Lynx 10G as well.
> 
> To avoid major noise in the lynx-28g driver, we keep compatibility shims
> (for now) where the old lynx_28g names are preserved, but translate to
> the common data structures.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean at nxp.com>

Reviewed-by: Ioana Ciornei <ioana.ciornei at nxp.com>