[PATCH v2 3/3] phy: qcom: qmp-pcie: Add QMP PCIe PHY support for Eliza

[Krishna Chaitanya Chundru]

On 6/7/2026 3:59 PM, Dmitry Baryshkov wrote:
> On Mon, Jun 01, 2026 at 10:59:46PM +0530, Krishna Chaitanya Chundru wrote:
>> Add QMP PCIe PHY support for the Eliza SoC. Introduce a new Gen3x1 PHY
>> configuration with Eliza-specific initialization tables, and reuse the
>> existing sm8550 Gen3x2 configuration for the Gen3x2 PHY instance.
>>
>> Also add the missing QPHY_PCIE_V6_PCS_PCIE_INT_AUX_CLK_CONFIG1 register
>> definition to the PCIe V6 PCS header.
>>
>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru at oss.qualcomm.com>
>> ---
>>  drivers/phy/qualcomm/phy-qcom-qmp-pcie.c        | 139 ++++++++++++++++++++++++
>>  drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h |   1 +
>>  2 files changed, 140 insertions(+)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> index fed2fc9bb311..257b4df965c3 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> @@ -198,6 +198,112 @@ static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
>>  	QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
>>  };
>>  
>> +static const struct qmp_phy_init_tbl eliza_qmp_gen3x1_pcie_serdes_tbl[] = {
> Thisis exactly the same as SM8550 table, except for three extra writes:
> QSERDES_V6_COM_VCO_TUNE1_MODE0, QSERDES_V6_COM_VCO_TUNE1_MODE1 and
> QSERDES_V6_COM_VCO_TUNE2_MODE1. What are the default values for SM8550?
For sm8550, the default values are different than what eliza is expecting

*PCIE0_QSERDES_PLL_VCO_TUNE1_MODE1*-  0xA *PCIE0_QSERDES_PLL_VCO_TUNE1_MODE0*-
0x53 *PCIE0_QSERDES_PLL_VCO_TUNE2_MODE1*- 0x1

- Krishna Chaitanya.

>> +	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0xb4),
>> +	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x03),
>> +	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x24),
> Other than that, looks good to me.
>