[PATCH v15 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] The schema explicitly permits the CPHY bus-type, contradicting the commit message.
- [Medium] The `data-lanes` property lacks an `items: maximum: 3` constraint to restrict physical lane indexes.
- [Medium] The `clock-lanes` property is implicitly allowed in the schema despite being unsupported by hardware.
--

--- Patch [1]: [PATCH v15 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema ---
commit 2ff6f092cd049b723d7a175d8013e50897b62b79
Author: Bryan O'Donoghue <bryan.odonoghue at linaro.org>

dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema

Add a base schema for the MIPI CSI2 PHYs on Qualcomm SoCs. This PHY
supports both DPHY and CPHY operation. A special mode of DPHY operation -
called variously split-mode or combo-mode also allows for two sensors to be
connected to one PHY.

> diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
> new file mode 100644
> index 0000000000000..8aa6ad2723988
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
> @@ -0,0 +1,202 @@
[ ... ]
> +        patternProperties:
> +          "^endpoint(@[01])?$":
> +            $ref: /schemas/media/video-interfaces.yaml#
> +            unevaluatedProperties: false
> +            properties:

[Severity: Medium]
Since this endpoint includes a reference to video-interfaces.yaml, the
clock-lanes property is implicitly evaluated and permitted. The description
below notes "The dedicated clock lane is not described", so should
clock-lanes: false be added here to explicitly forbid it?

> +              bus-type:
> +                enum:
> +                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
> +                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY

[Severity: Medium]
The commit message explicitly states "CPHY is left to future work", but the
schema permits the CPHY bus-type here. 

Does this allow device trees with incomplete or invalid CPHY configurations
to silently pass schema validation?

> +
> +              data-lanes:
> +                minItems: 1
> +                maxItems: 4
> +                description:
> +                  An array of physical data lane indexes, 0-3, following the

[Severity: Medium]
Should there be an explicit items constraint (e.g., items: { maximum: 3 })
added to enforce the 0-3 range for physical lane indexes?

Without it, the array values fall back to the /schemas/media/video-interfaces.yaml#
default constraint, which allows physical lane values up to 8.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260730-x1e-csi2-phy-v15-0-f284131de1fa@linaro.org?part=1