[PATCH v8 06/12] clk: zte: Add regmap-based clocks
Brian Masney
bmasney at redhat.com
Tue Jul 28 06:42:06 PDT 2026
On Mon, Jul 27, 2026 at 09:24:21PM +0300, Stefan Dösinger wrote:
> This is based on meson/clk-regmap.c, although slightly simplified. I
> have kept the copyright lines at the top of the file to indicate its
> origin.
>
> I see that numerous clock drivers have their own incarnation of regmap-
> based mux/div/gate clocks. If there is any version of it that is likely
> to be elevated to shared code like clk-gate.c I'll copy that and try to
> use it as unmodified as possible.
>
> Signed-off-by: Stefan Dösinger <stefandoesinger at gmail.com>
>
> ---
>
> Version 8: Use ZX297520V3_CLK_NO_EXPORT instead of 0 for unexported clocks.
>
> Version 6: Remove stray regmap (Sashiko)
>
> Version 5: Use regmap_test_bits in zte_clk_regmap_gate_is_enabled
> ---
> drivers/clk/zte/clk-regmap.c | 218 ++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 215 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/zte/clk-regmap.c b/drivers/clk/zte/clk-regmap.c
> index 984abeb45ab2..671b81bcda4d 100644
> --- a/drivers/clk/zte/clk-regmap.c
> +++ b/drivers/clk/zte/clk-regmap.c
> @@ -7,28 +7,240 @@
> */
>
> #include <linux/clk-provider.h>
> +#include <linux/container_of.h>
> #include <linux/device.h>
> #include <linux/regmap.h>
> +#include <linux/types.h>
> #include <linux/errno.h>
> +#include <linux/bits.h>
> +#include <linux/err.h>
>
> #include "clk-zx.h"
>
> +struct zte_clk_regmap {
> + struct clk_hw hw;
> + struct regmap *map;
> + u16 reg;
> + u8 shift;
> + u8 size;
> +};
> +
> +static inline struct zte_clk_regmap *to_zte_clk_regmap(struct clk_hw *hw)
> +{
> + return container_of(hw, struct zte_clk_regmap, hw);
> +}
> +
> +static int zte_clk_regmap_gate_enable(struct clk_hw *hw)
> +{
> + struct zte_clk_regmap *clk = to_zte_clk_regmap(hw);
> +
> + return regmap_set_bits(clk->map, clk->reg, BIT(clk->shift));
> +}
> +
> +static void zte_clk_regmap_gate_disable(struct clk_hw *hw)
> +{
> + struct zte_clk_regmap *clk = to_zte_clk_regmap(hw);
> +
> + regmap_clear_bits(clk->map, clk->reg, BIT(clk->shift));
> +}
> +
> +static int zte_clk_regmap_gate_is_enabled(struct clk_hw *hw)
> +{
> + struct zte_clk_regmap *clk = to_zte_clk_regmap(hw);
> +
> + return regmap_test_bits(clk->map, clk->reg, BIT(clk->shift));
> +}
> +
> +static const struct clk_ops zte_clk_regmap_gate_ops = {
> + .enable = zte_clk_regmap_gate_enable,
> + .disable = zte_clk_regmap_gate_disable,
> + .is_enabled = zte_clk_regmap_gate_is_enabled,
> +};
> +
> int zx_clk_register_gates(struct device *dev, struct regmap *regmap,
> const struct zx_gate_desc *desc, unsigned int num,
> struct clk_hw_onecell_data *clocks)
> {
> - return -ENODEV;
> + struct zte_clk_regmap *clk;
> + unsigned int i;
> + int res;
> +
> + for (i = 0; i < num; ++i) {
> + struct clk_init_data init = {};
> +
> + clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
> + if (!clk)
> + return -ENOMEM;
> +
> + init.name = desc[i].name;
> + init.ops = &zte_clk_regmap_gate_ops;
> + init.parent_names = &desc[i].parent;
> + init.num_parents = 1;
> + init.flags = CLK_SET_RATE_PARENT | desc[i].flags;
> + clk->hw.init = &init;
> + clk->map = regmap;
> + clk->reg = desc[i].reg;
> + clk->shift = desc[i].shift;
> + clk->size = 1;
> +
> + res = devm_clk_hw_register(dev, &clk->hw);
> + if (res)
> + return dev_err_probe(dev, res, "Failed to register clk %s\n", desc[i].name);
> +
> + if (desc[i].id != ZX297520V3_CLK_NO_EXPORT)
> + clocks->hws[desc[i].id] = &clk->hw;
> + }
> +
> + return 0;
> +}
> +
> +static unsigned long zte_clk_regmap_div_recalc_rate(struct clk_hw *hw,
> + unsigned long prate)
> +{
> + struct zte_clk_regmap *clk = to_zte_clk_regmap(hw);
> + unsigned int val;
> + int ret;
> +
> + ret = regmap_read(clk->map, clk->reg, &val);
> + if (ret)
> + /* Gives a hint that something is wrong */
> + return 0;
> +
> + val >>= clk->shift;
> + val &= clk_div_mask(clk->size);
> + return divider_recalc_rate(hw, prate, val, NULL, 0, clk->size);
Newline before the return
> +}
> +
> +static int zte_clk_regmap_div_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + struct zte_clk_regmap *clk = to_zte_clk_regmap(hw);
> +
> + return divider_determine_rate(hw, req, NULL, clk->size, 0);
> +}
> +
> +static int zte_clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct zte_clk_regmap *clk = to_zte_clk_regmap(hw);
> + unsigned int val;
> + int ret;
> +
> + ret = divider_get_val(rate, parent_rate, NULL, clk->size, 0);
> + if (ret < 0)
> + return ret;
> +
> + val = (unsigned int)ret << clk->shift;
> + return regmap_update_bits(clk->map, clk->reg, clk_div_mask(clk->size) << clk->shift, val);
> }
>
> +static const struct clk_ops zte_clk_regmap_divider_ops = {
> + .recalc_rate = zte_clk_regmap_div_recalc_rate,
> + .determine_rate = zte_clk_regmap_div_determine_rate,
> + .set_rate = zte_clk_regmap_div_set_rate,
> +};
> +
> int zx_clk_register_dividers(struct device *dev, struct regmap *regmap,
> const struct zx_div_desc *desc, unsigned int num)
> {
> - return -ENODEV;
> + struct zte_clk_regmap *clk;
> + unsigned int i;
> + int res;
> +
> + for (i = 0; i < num; ++i) {
> + struct clk_init_data init = {};
> +
> + clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
> + if (!clk)
> + return -ENOMEM;
> +
> + init.name = desc[i].name;
> + init.ops = &zte_clk_regmap_divider_ops;
> + init.parent_names = &desc[i].parent;
Use parent_data instead of parent_names
> + init.num_parents = 1;
> + init.flags = CLK_SET_RATE_PARENT;
> + clk->hw.init = &init;
> + clk->map = regmap;
> + clk->reg = desc[i].reg;
> + clk->shift = desc[i].shift;
> + clk->size = desc[i].size;
> +
> + res = devm_clk_hw_register(dev, &clk->hw);
> + if (res)
> + return dev_err_probe(dev, res, "Failed to register clk %s\n", desc[i].name);
> + }
> +
> + return 0;
> }
>
> +static u8 zte_clk_regmap_mux_get_parent(struct clk_hw *hw)
> +{
> + struct zte_clk_regmap *clk = to_zte_clk_regmap(hw);
> + unsigned int val;
> + int ret;
> +
> + ret = regmap_read(clk->map, clk->reg, &val);
> + if (ret)
> + return 0xff;
> +
> + val >>= clk->shift;
> + val &= GENMASK(clk->size - 1, 0);
> + return clk_mux_val_to_index(hw, NULL, 0, val);
> +}
> +
> +static int zte_clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index)
> +{
> + struct zte_clk_regmap *clk = to_zte_clk_regmap(hw);
> + unsigned int val = clk_mux_index_to_val(NULL, 0, index);
> +
> + return regmap_update_bits(clk->map, clk->reg,
> + GENMASK(clk->size - 1, 0) << clk->shift,
> + val << clk->shift);
> +}
> +
> +static int zte_clk_regmap_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
> +{
> + return clk_mux_determine_rate_flags(hw, req, 0);
> +}
> +
> +static const struct clk_ops zte_clk_regmap_mux_ops = {
> + .get_parent = zte_clk_regmap_mux_get_parent,
> + .set_parent = zte_clk_regmap_mux_set_parent,
> + .determine_rate = zte_clk_regmap_mux_determine_rate,
> +};
> +
> int zx_clk_register_muxes(struct device *dev, struct regmap *regmap,
> const struct zx_mux_desc *desc, unsigned int num,
> struct clk_hw_onecell_data *clocks)
> {
> - return -ENODEV;
> + struct zte_clk_regmap *clk;
> + unsigned int i;
> + int res;
> +
> + for (i = 0; i < num; ++i) {
> + struct clk_init_data init = {};
> +
> + clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
> + if (!clk)
> + return -ENOMEM;
> +
> + init.name = desc[i].name;
> + init.ops = &zte_clk_regmap_mux_ops;
> + init.parent_names = desc[i].parents;
Use parent_data instead of parent_names
Brian
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