[PATCH v8 05/12] clk: zte: Add Clock registration infrastructure
Brian Masney
bmasney at redhat.com
Tue Jul 28 06:38:54 PDT 2026
Hi Stefan,
On Mon, Jul 27, 2026 at 09:24:20PM +0300, Stefan Dösinger wrote:
> The next patches will implement the regmap clocks and PLL driver. The
> actual hardware specific clock listing will live in a separate module.
>
> Signed-off-by: Stefan Dösinger <stefandoesinger at gmail.com>
>
> ---
>
> Version 8:
> Use ZX297520V3_CLK_NO_EXPORT=(~0u) for unexported clocks. While using 0,
> and starting clock indices at 1, is a common pattern in existing
> drivers, it exposes a driver implementation detail in the hardware
> binding interface.
>
> If desired, I can change the special index to a separate field in the
> structs.
>
> Fix the return value if the ->init() callback fails. (Sashiko)
>
> Version 7:
> *) Add fixed dividers to handle PLL subdivisions
> *) Never register PLLs directly as exported clocks - everything on this
> SoC goes through a gate before it leaves a controller.
>
> Version 6:
> *) Remove auxdev now that LSP clocks also use MFD
> *) Error codepath fixes pointed out by Sashiko.
>
> Version 5:
>
> *) Pass the static clk data instead of calling get_match_data to prepare
> for operating as an MFD child.
>
> *) Don't use devm_kzalloc to allocate the auxiliary_device
> structure. I guess Sashiko is right, and that's what "Because once the
> device is placed on the bus the parent driver can not tell what other
> code may have a reference to this data" is trying to tell me.
>
> *) Fix error check for device_node_to_regmap.
> ---
> MAINTAINERS | 1 +
> drivers/clk/Kconfig | 1 +
> drivers/clk/Makefile | 1 +
> drivers/clk/zte/Kconfig | 16 +++++
> drivers/clk/zte/Makefile | 5 ++
> drivers/clk/zte/clk-regmap.c | 34 ++++++++++
> drivers/clk/zte/clk-zx.c | 155 +++++++++++++++++++++++++++++++++++++++++++
> drivers/clk/zte/clk-zx.h | 91 +++++++++++++++++++++++++
> drivers/clk/zte/pll-zx.c | 16 +++++
> 9 files changed, 320 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b04e9d43cfb0..692f005cb2c4 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3883,6 +3883,7 @@ F: Documentation/devicetree/bindings/clock/zte,zx297520v3-matrixcrm.yaml
> F: Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.yaml
> F: arch/arm/boot/dts/zte/
> F: arch/arm/mach-zte/
> +F: drivers/clk/zte/
> F: drivers/mfd/zte-zx297520v3-crm.c
> F: include/dt-bindings/clock/zte,zx297520v3-clk.h
> F: include/dt-bindings/phy/zte,zx297520v3-topcrm.h
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 1717ce75a907..6f0a863951ca 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -545,6 +545,7 @@ source "drivers/clk/uniphier/Kconfig"
> source "drivers/clk/visconti/Kconfig"
> source "drivers/clk/x86/Kconfig"
> source "drivers/clk/xilinx/Kconfig"
> +source "drivers/clk/zte/Kconfig"
> source "drivers/clk/zynqmp/Kconfig"
>
> # Kunit test cases
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index cc108a75a900..13a5478f1112 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -167,5 +167,6 @@ ifeq ($(CONFIG_COMMON_CLK), y)
> obj-$(CONFIG_X86) += x86/
> endif
> obj-y += xilinx/
> +obj-$(CONFIG_COMMON_CLK_ZTE) += zte/
> obj-$(CONFIG_ARCH_ZYNQ) += zynq/
> obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/
> diff --git a/drivers/clk/zte/Kconfig b/drivers/clk/zte/Kconfig
> new file mode 100644
> index 000000000000..0222549dd211
> --- /dev/null
> +++ b/drivers/clk/zte/Kconfig
> @@ -0,0 +1,16 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +#
> +# ZTE Clock Drivers
> +#
> +
> +config COMMON_CLK_ZTE
> + tristate "Clock driver for ZTE SoCs"
> + depends on ARCH_ZTE || COMPILE_TEST
> + default ARCH_ZTE
> + select MFD_SYSCON
> + help
> + This option selects common clock infrastructure for ZTE based SoCs.
> + You will need to enable one or more SoC specific drivers to make use
> + of this.
> +
> + Enable this if you are building a kernel for a ZTE designed board.
> diff --git a/drivers/clk/zte/Makefile b/drivers/clk/zte/Makefile
> new file mode 100644
> index 000000000000..27db07293165
> --- /dev/null
> +++ b/drivers/clk/zte/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +
> +obj-$(CONFIG_COMMON_CLK_ZTE) += clk-zte.o
> +
> +clk-zte-y += clk-zx.o pll-zx.o clk-regmap.o
> diff --git a/drivers/clk/zte/clk-regmap.c b/drivers/clk/zte/clk-regmap.c
> new file mode 100644
> index 000000000000..984abeb45ab2
> --- /dev/null
> +++ b/drivers/clk/zte/clk-regmap.c
> @@ -0,0 +1,34 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2014 MediaTek Inc.
> + * Copyright (c) 2018 BayLibre, SAS.
> + * Copyright (c) 2026 Stefan Dösinger.
> + * Author: Stefan Dösinger <stefandoesinger at gmail.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/device.h>
> +#include <linux/regmap.h>
> +#include <linux/errno.h>
Sort the headers.
> +
> +#include "clk-zx.h"
> +
> +int zx_clk_register_gates(struct device *dev, struct regmap *regmap,
> + const struct zx_gate_desc *desc, unsigned int num,
> + struct clk_hw_onecell_data *clocks)
> +{
> + return -ENODEV;
> +}
> +
> +int zx_clk_register_dividers(struct device *dev, struct regmap *regmap,
> + const struct zx_div_desc *desc, unsigned int num)
> +{
> + return -ENODEV;
> +}
> +
> +int zx_clk_register_muxes(struct device *dev, struct regmap *regmap,
> + const struct zx_mux_desc *desc, unsigned int num,
> + struct clk_hw_onecell_data *clocks)
> +{
> + return -ENODEV;
> +}
> diff --git a/drivers/clk/zte/clk-zx.c b/drivers/clk/zte/clk-zx.c
> new file mode 100644
> index 000000000000..c9e9048d3ade
> --- /dev/null
> +++ b/drivers/clk/zte/clk-zx.c
> @@ -0,0 +1,155 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2026 Stefan Dösinger
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/errno.h>
> +#include <linux/clk.h>
> +#include <linux/err.h>
Also sort the headers.
> +
> +#include "clk-zx.h"
> +
> +static int zx_clk_register_fixed_dividers(struct device *dev, struct regmap *regmap,
> + const struct zx_fixed_divider_desc *desc,
> + unsigned int num)
> +{
> + struct clk_hw *clk;
> + unsigned int i;
> +
> + for (i = 0; i < num; ++i) {
> + clk = devm_clk_hw_register_fixed_factor(dev, desc[i].name, desc[i].parent,
> + CLK_SET_RATE_PARENT, 1, desc[i].div);
> + if (IS_ERR(clk)) {
The { } is not needed here.
> + return dev_err_probe(dev, PTR_ERR(clk), "Failed to register clk %s\n",
> + desc[i].name);
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void zx_delete_clk_provider(void *data)
> +{
> + of_clk_del_provider(data);
> +}
> +
> +static void zx_clk_disable_unprepare_put(void *data)
> +{
> + clk_disable_unprepare(data);
> + clk_put(data);
> +}
> +
> +int zx_clk_common_probe(struct device *dev, struct device_node *of_node,
> + const struct zx_clk_data *data)
> +{
> + unsigned int public_clk_count = 0, highest_id = 0;
> + struct clk_hw_onecell_data *clocks;
> + struct regmap *map;
> + struct clk *clk;
> + unsigned int i;
> + int res;
> +
> + map = device_node_to_regmap(of_node);
> + if (IS_ERR(map))
> + return PTR_ERR(map);
> +
> + for (i = 0; i < data->num_muxes; ++i) {
> + if (data->muxes[i].id != ZX297520V3_CLK_NO_EXPORT) {
> + if (data->muxes[i].id > highest_id)
> + highest_id = data->muxes[i].id;
> + public_clk_count++;
> + }
> + }
> + for (i = 0; i < data->num_gates; ++i) {
> + if (data->gates[i].id != ZX297520V3_CLK_NO_EXPORT) {
> + if (data->gates[i].id > highest_id)
> + highest_id = data->gates[i].id;
> + public_clk_count++;
> + }
> + }
> +
> + if (WARN_ON(public_clk_count != highest_id + 1))
> + return -EINVAL;
> +
> + clocks = devm_kzalloc(dev, struct_size(clocks, hws, public_clk_count), GFP_KERNEL);
> + if (!clocks)
> + return -ENOMEM;
> + clocks->num = public_clk_count;
> +
> + for (i = 0; i < data->num_inputs_enable; ++i) {
> + clk = of_clk_get_by_name(of_node, data->inputs_enable[i]);
> + if (IS_ERR(clk)) {
> + return dev_err_probe(dev, PTR_ERR(clk), "Input clk %s failure\n",
> + data->inputs_enable[i]);
> + }
> +
> + res = clk_prepare_enable(clk);
> + if (res) {
> + clk_put(clk);
> + return dev_err_probe(dev, res, "Input clk %s enable failure\n",
> + data->inputs_enable[i]);
> + }
> + res = devm_add_action_or_reset(dev, zx_clk_disable_unprepare_put, clk);
> + if (res)
> + return res;
> + }
> + for (i = 0; i < data->num_inputs; ++i) {
> + /* FIXME: devm_get_clk_from_child doesn't do any tree traversal, so it works here
> + * whether "of_node" belongs to "dev" or a parent of "dev". Is it supposed to be
> + * used that way though?
> + */
> + clk = devm_get_clk_from_child(dev, of_node, data->inputs[i]);
I don't know the intention of the original function without digging into
the history. Can you just use of_clk_get_by_name(of_node, data->inputs[i])
like you do in the for loop above for consistency?
> + if (IS_ERR(clk)) {
> + return dev_err_probe(dev, PTR_ERR(clk), "Input clk %s failure\n",
> + data->inputs[i]);
> + }
> + }
> +
> + if (data->init) {
> + res = data->init(map);
> + if (res)
> + return res;
> + }
> +
> + res = zx_clk_register_fixed_dividers(dev, map, data->fixed_divs, data->num_fixed_divs);
> + if (res)
> + return res;
> +
> + res = zx_clk_register_plls(dev, map, data->plls, data->num_plls);
> + if (res)
> + return res;
> +
> + res = zx_clk_register_muxes(dev, map, data->muxes, data->num_muxes, clocks);
> + if (res)
> + return res;
> +
> + res = zx_clk_register_dividers(dev, map, data->divs, data->num_divs);
> + if (res)
> + return res;
> +
> + res = zx_clk_register_gates(dev, map, data->gates, data->num_gates, clocks);
> + if (res)
> + return res;
> +
> + /* This is to catch holes in the tables rather than registration errors. The count vs
> + * highest ID should catch most static issues. This check here will trigger if an ID is
> + * reused by accident.
> + */
Comments need to be:
/*
* This is to ...
*/
> + for (i = 0; i < public_clk_count; i++) {
> + if (WARN(!clocks->hws[i], "Clock %u not registered\n", i))
> + return -EINVAL;
> + }
> +
> + res = of_clk_add_hw_provider(of_node, of_clk_hw_onecell_get, clocks);
> + if (res)
> + return res;
> + return devm_add_action_or_reset(dev, zx_delete_clk_provider, of_node);
Use the devm_of_clk_add_hw_provider()
Brian
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