[PATCH v8 03/12] dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller
Stefan Dösinger
stefandoesinger at gmail.com
Mon Jul 27 11:24:18 PDT 2026
The clock controller of the zx297520v3 Low Speed Peripherals is
relatively clean. One register per device with gates, muxes and resets
and for some devices a divider. There are even bits in the matrix
controller to control propagation of clock lines down to LSP.
The clocks are sorted by register address and I am convinced that the
device list is complete. There are, however, a few more registers that
are likely extra dividers for TDM and I2S devices.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at oss.qualcomm.com>
Signed-off-by: Stefan Dösinger <stefandoesinger at gmail.com>
---
Patch changelog:
v8:
*) Start clock indices at 0
*) A minor grammar fix in the second paragraph of the binding prose
v5:
Rename from lspclk to lspcrm
Remove matrixcrm from example
v4: Order properties compatible->reg->clocks->clock->names->#cells
---
.../bindings/clock/zte,zx297520v3-lspcrm.yaml | 101 +++++++++++++++++++++
MAINTAINERS | 1 +
include/dt-bindings/clock/zte,zx297520v3-clk.h | 37 ++++++++
include/dt-bindings/reset/zte,zx297520v3-reset.h | 19 ++++
4 files changed, 158 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.yaml b/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.yaml
new file mode 100644
index 000000000000..cfad0e0372f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/zte,zx297520v3-lspcrm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ZTE zx297520v3 SoC LSP clock and reset controller
+
+maintainers:
+ - Stefan Dösinger <stefandoesinger at gmail.com>
+
+description: |
+ This clock and reset controller controls low speed peripherals on the board.
+ This is a relatively isolated subsystem containing UART, I2C, I2S and SPI
+ devices. The controller is responsible for bringing the devices out of reset
+ and enabling their clocks as needed.
+
+ The controller receives its clock signals from the matrix controller, and
+ these signals need to be declared as clock inputs.
+
+ All available clocks are defined as preprocessor macros in the
+ "include/dt-bindings/clock/zte,zx297520v3-clk.h" header. Resets are defined in
+ the "include/dt-bindings/reset/zte,zx297520v3-reset.h" header.
+
+properties:
+ compatible:
+ const: zte,zx297520v3-lspcrm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main PLL divided by 5 output from matrixcrm (124.8 MHz)
+ - description: Main PLL divided by 4 output from matrixcrm (156 MHz)
+ - description: Main PLL divided by 6 output from matrixcrm (104 MHz)
+ - description: Main PLL divided by 8 output from matrixcrm (78 MHz)
+ - description: Main PLL divided by 12 output from matrixcrm (52 MHz)
+ - description: Main oscillator output from matrixcrm (26 MHz)
+ - description: Timer oscillator output from matrixcrm (32 kHz)
+ - description: LSP pclk output from matrixcrm (26 MHz)
+ - description: TDM wclk mux output from matrixcrm
+ - description: DPLL divided by 4 output from matrixcrm (122.88 MHz)
+
+ clock-names:
+ items:
+ - const: mpll-d5
+ - const: mpll-d4
+ - const: mpll-d6
+ - const: mpll-d8
+ - const: mpll-d12
+ - const: osc26m
+ - const: osc32k
+ - const: pclk
+ - const: tdm-wclk
+ - const: dpll-d4
+
+ resets:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/zte,zx297520v3-clk.h>
+ #include <dt-bindings/reset/zte,zx297520v3-reset.h>
+
+ clock-controller at 1400000 {
+ compatible = "zte,zx297520v3-lspcrm";
+ reg = <0x01400000 0x100>;
+ clocks = <&matrixcrm ZX297520V3_LSP_MPLL_D5_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_MPLL_D4_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_MPLL_D6_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_MPLL_D8_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_MPLL_D12_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_OSC26M_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_OSC32K_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_PCLK>,
+ <&matrixcrm ZX297520V3_LSP_TDM_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_DPLL_D4_WCLK>;
+ clock-names = "mpll-d5", "mpll-d4", "mpll-d6", "mpll-d8", "mpll-d12",
+ "osc26m", "osc32k", "pclk", "tdm-wclk", "dpll-d4";
+ resets = <&matrixcrm ZX297520V3_LSP_RESET>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index dc2972ade70f..05322672b9b5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3878,6 +3878,7 @@ L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
S: Odd fixes
F: Documentation/arch/arm/zte/
F: Documentation/devicetree/bindings/arm/zte.yaml
+F: Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.yaml
F: Documentation/devicetree/bindings/clock/zte,zx297520v3-matrixcrm.yaml
F: Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.yaml
F: arch/arm/boot/dts/zte/
diff --git a/include/dt-bindings/clock/zte,zx297520v3-clk.h b/include/dt-bindings/clock/zte,zx297520v3-clk.h
index a8477e9b2a14..8824740468a3 100644
--- a/include/dt-bindings/clock/zte,zx297520v3-clk.h
+++ b/include/dt-bindings/clock/zte,zx297520v3-clk.h
@@ -104,4 +104,41 @@
#define ZX297520V3_SRAM0_PCLK 38
#define ZX297520V3_GSM_CFG_PCLK 39
+#define ZX297520V3_TIMER_L1_WCLK 0
+#define ZX297520V3_TIMER_L1_PCLK 1
+#define ZX297520V3_WDT_L2_WCLK 2
+#define ZX297520V3_WDT_L2_PCLK 3
+#define ZX297520V3_WDT_L3_WCLK 4
+#define ZX297520V3_WDT_L3_PCLK 5
+#define ZX297520V3_PWM_WCLK 6
+#define ZX297520V3_PWM_PCLK 7
+#define ZX297520V3_I2S0_WCLK 8
+#define ZX297520V3_I2S0_PCLK 9
+#define ZX297520V3_I2S1_WCLK 10
+#define ZX297520V3_I2S1_PCLK 11
+#define ZX297520V3_QSPI_WCLK 12
+#define ZX297520V3_QSPI_PCLK 13
+#define ZX297520V3_UART1_WCLK 14
+#define ZX297520V3_UART1_PCLK 15
+#define ZX297520V3_I2C1_WCLK 16
+#define ZX297520V3_I2C1_PCLK 17
+#define ZX297520V3_SPI0_WCLK 18
+#define ZX297520V3_SPI0_PCLK 19
+#define ZX297520V3_TIMER_LB_WCLK 20
+#define ZX297520V3_TIMER_LB_PCLK 21
+#define ZX297520V3_TIMER_LC_WCLK 22
+#define ZX297520V3_TIMER_LC_PCLK 23
+#define ZX297520V3_UART2_WCLK 24
+#define ZX297520V3_UART2_PCLK 25
+#define ZX297520V3_WDT_LE_WCLK 26
+#define ZX297520V3_WDT_LE_PCLK 27
+#define ZX297520V3_TIMER_LF_WCLK 28
+#define ZX297520V3_TIMER_LF_PCLK 29
+#define ZX297520V3_SPI1_WCLK 30
+#define ZX297520V3_SPI1_PCLK 31
+#define ZX297520V3_TIMER_L11_WCLK 32
+#define ZX297520V3_TIMER_L11_PCLK 33
+#define ZX297520V3_TDM_WCLK 34
+#define ZX297520V3_TDM_PCLK 35
+
#endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */
diff --git a/include/dt-bindings/reset/zte,zx297520v3-reset.h b/include/dt-bindings/reset/zte,zx297520v3-reset.h
index 4682d4a599c6..69eef84b2f29 100644
--- a/include/dt-bindings/reset/zte,zx297520v3-reset.h
+++ b/include/dt-bindings/reset/zte,zx297520v3-reset.h
@@ -41,4 +41,23 @@
#define ZX297520V3_VOU_RESET 9
#define ZX297520V3_LSP_RESET 10
+#define ZX297520V3_TIMER_L1_RESET 0
+#define ZX297520V3_WDT_L2_RESET 1
+#define ZX297520V3_WDT_L3_RESET 2
+#define ZX297520V3_PWM_RESET 3
+#define ZX297520V3_I2S0_RESET 4
+#define ZX297520V3_I2S1_RESET 5
+#define ZX297520V3_QSPI_RESET 6
+#define ZX297520V3_UART1_RESET 7
+#define ZX297520V3_I2C1_RESET 8
+#define ZX297520V3_SPI0_RESET 9
+#define ZX297520V3_TIMER_LB_RESET 10
+#define ZX297520V3_TIMER_LC_RESET 11
+#define ZX297520V3_UART2_RESET 12
+#define ZX297520V3_WDT_LE_RESET 13
+#define ZX297520V3_TIMER_LF_RESET 14
+#define ZX297520V3_SPI1_RESET 15
+#define ZX297520V3_TIMER_L11_RESET 16
+#define ZX297520V3_TDM_RESET 17
+
#endif /* __DT_BINDINGS_RESET_ZX297520V3_H */
--
2.54.0
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