[PATCH v6 5/6] arm64: dts: qcom: mahua: Replace pcie3a/pcie3_phy with dedicated pcie3b_phy

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The newly added `pcie3b_phy` node lacks the `vdda-phy-supply` and `vdda-pll-supply` properties, which will trigger `dtbs_check` errors.
--

--- Patch [5]: [PATCH v6 5/6] arm64: dts: qcom: mahua: Replace pcie3a/pcie3_phy with dedicated pcie3b_phy ---
commit 919bcfc5a66ac884962879da8e57f8559595dcdf
Author: Qiang Yu <qiang.yu at oss.qualcomm.com>

arm64: dts: qcom: mahua: Replace pcie3a/pcie3_phy with dedicated pcie3b_phy

This patch removes the unused pcie3a and shared pcie3_phy nodes from the 
Mahua device tree, as it only uses PCIe3b. It replaces them with a dedicated 
pcie3b_phy node using the existing Gen5x4 PHY compatible, and updates the 
GCC pipe clock parent and PCIe3b port phy references accordingly.

> diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom/mahua.dtsi
> index 22822b6b2e8b9..3280eb96d61c0 100644
> --- a/arch/arm64/boot/dts/qcom/mahua.dtsi
> +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi
[ ... ]
> @@ -134,6 +186,43 @@ &pcie_west_slv_noc {
>  	compatible = "qcom,mahua-pcie-west-slv-noc";
>  };
>  
> +&soc {
> +	pcie3b_phy: phy at 1b90000 {
> +		compatible = "qcom,glymur-qmp-gen5x4-pcie-phy";
> +		reg = <0x0 0x01b90000 0x0 0x10000>;

[Severity: Low]
Does this node need to define vdda-phy-supply and vdda-pll-supply?

The qcom,glymur-qmp-gen5x4-pcie-phy compatible requires these properties
according to the bindings schema. Without them, this might trigger
schema validation failures during make dtbs_check.

> +
> +		clocks = <&gcc GCC_PCIE_PHY_3B_AUX_CLK>,
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260722-glymur_linkmode_0722-v6-0-bba8156b8cbb@oss.qualcomm.com?part=5