[PATCH v6 1/6] dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The commit message claims to add the file `qcom,glymur-qmp-pcie-multiphy.yaml`, but the patch actually adds `qcom,glymur-qmp-gen5x8-pcie-phy.yaml`.
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--- Patch [1]: [PATCH v6 1/6] dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY ---
commit daff94211d78815eee9a0fc0796f4b5fb3719b59
Author: Qiang Yu <qiang.yu at oss.qualcomm.com>

dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY

This commit adds a standalone device tree binding for the Glymur Gen5 PCIe
PHY hardware block. It describes a PHY controller supporting both x8 and
x4+x4 link modes selected at runtime via a TCSR syscon register.

> dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY
> 
> Add qcom,glymur-qmp-pcie-multiphy.yaml as a standalone binding
> for the Glymur Gen5 PCIe PHY hardware block. This block supports two
> link modes, selected at runtime via a TCSR syscon register:

[Severity: Medium]
Does the commit message reference the wrong filename? 

The message states the new file is named qcom,glymur-qmp-pcie-multiphy.yaml,
but the diff actually creates qcom,glymur-qmp-gen5x8-pcie-phy.yaml:

> diff --git a/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml
> new file mode 100644
> index 0000000000000..759f7f979dc6a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml

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Sashiko AI review · https://sashiko.dev/#/patchset/20260722-glymur_linkmode_0722-v6-0-bba8156b8cbb@oss.qualcomm.com?part=1