[RESEND PATCH 0/3] phy: zynqmp: fix SERDES scrambler register handling and enable for USB

[Michal Simek]

On 6/27/26 17:52, Radhey Shyam Pandey wrote:
> This series fixes three related issues in the ZynqMP SERDES PHY
> scrambler/encoder bypass path:
> 
> 1. The L0_TM_DISABLE_SCRAMBLE_ENCODER mask incorrectly included bit 2
>     of L0_TX_DIG_61, which is a reserved read-only field. Correct the
>     mask to (BIT(3) | GENMASK(1, 0)).
> 
> 2. xpsgtr_bypass_scrambler_8b10b() used xpsgtr_write_phy() which
>     performs a full register write, clobbering unrelated bits. Switch
>     to xpsgtr_clr_set_phy() with clr=mask, set=mask to preserve other
>     register fields.
> 
> 3. USB Gen1 requires PHY-side scrambling and 8b/10b encoding as
>     mandated by the USB 3.x specification. The driver was incorrectly
>     bypassing these for USB, the same as SATA and SGMII where encoding
>     is handled in the controller.
> 
> Issues reported by sashiko[1] are pre-existing issues and will
> taken as separate followup series.
> 
> [1]:
> https://lore.kernel.org/all/20260512213513.852EEC2BCB0@smtp.kernel.org
> https://lore.kernel.org/all/20260512223142.1AFC4C2BCB0@smtp.kernel.org
> 
> Nava kishore Manne (3):
>    phy: zynqmp: fix L0_TM_DISABLE_SCRAMBLE_ENCODER mask
>    phy: zynqmp: use read-modify-write for SERDES scrambler bypass
>    phy: zynqmp: keep SERDES scrambler and 8b/10b enabled for USB
> 
>   drivers/phy/xilinx/phy-zynqmp.c | 37 ++++++++++++++++++++++++++-------
>   1 file changed, 30 insertions(+), 7 deletions(-)
> 
> 
> base-commit: 3d5670d672ae08b8c534b7beed6f57c8b44e7b43

Acked-by: Michal Simek <michal.simek at amd.com>

Vinod: Can you please pick it up?

Thanks,
Michal