[PATCH v4 2/2] phy: qcom-qmp-ufs: Add UFS PHY support on Hawi
Palash Kambar
palash.kambar at oss.qualcomm.com
Fri Jul 10 04:58:38 PDT 2026
On 6/17/2026 11:30 AM, Manivannan Sadhasivam wrote:
> On Mon, Jun 15, 2026 at 02:42:42PM +0530, palash.kambar at oss.qualcomm.com wrote:
>> From: Palash Kambar <palash.kambar at oss.qualcomm.com>
>>
>> Add the init sequence tables and config for the UFS QMP phy found in
>> the Hawi SoC.
>>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov at oss.qualcomm.com>
>> Signed-off-by: Palash Kambar <palash.kambar at oss.qualcomm.com>
>
> Reviewed-by: Manivannan Sadhasivam <mani at kernel.org>
>
> - Mani
>
>> ---
>> .../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v7.h | 24 +++
>> .../qualcomm/phy-qcom-qmp-qserdes-com-v8.h | 13 +-
>> .../phy-qcom-qmp-qserdes-txrx-ufs-v8.h | 37 +++++
>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 139 ++++++++++++++++++
>> 4 files changed, 212 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v7.h
>> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v8.h
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v7.h
>> new file mode 100644
>> index 000000000000..e80d3dd6a190
>> --- /dev/null
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v7.h
>> @@ -0,0 +1,24 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (c) 2026, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#ifndef QCOM_PHY_QMP_PCS_UFS_V7_H_
>> +#define QCOM_PHY_QMP_PCS_UFS_V7_H_
>> +
>> +/* Only for QMP V7 PHY - UFS PCS registers */
>> +#define QPHY_V7_PCS_UFS_PHY_START 0x000
>> +#define QPHY_V7_PCS_UFS_POWER_DOWN_CONTROL 0x004
>> +#define QPHY_V7_PCS_UFS_SW_RESET 0x008
>> +#define QPHY_V7_PCS_UFS_PCS_CTRL1 0x01C
>> +#define QPHY_V7_PCS_UFS_PLL_CNTL 0x028
>> +#define QPHY_V7_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02C
>> +#define QPHY_V7_PCS_UFS_TX_HSGEAR_CAPABILITY 0x060
>> +#define QPHY_V7_PCS_UFS_RX_HSGEAR_CAPABILITY 0x094
>> +#define QPHY_V7_PCS_UFS_LINECFG_DISABLE 0x140
>> +#define QPHY_V7_PCS_UFS_RX_SIGDET_CTRL2 0x150
>> +#define QPHY_V7_PCS_UFS_READY_STATUS 0x16c
>> +#define QPHY_V7_PCS_UFS_TX_MID_TERM_CTRL1 0x1b8
>> +#define QPHY_V7_PCS_UFS_MULTI_LANE_CTRL1 0x1c0
>> +
>> +#endif
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h
>> index d8ac4c4a2c31..d416113bcb3c 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h
>> @@ -1,6 +1,6 @@
>> /* SPDX-License-Identifier: GPL-2.0 */
>> /*
>> - * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
>> + * Copyright (c) 2026, The Linux Foundation. All rights reserved.
>> */
>>
>> #ifndef QCOM_PHY_QMP_QSERDES_COM_V8_H_
>> @@ -71,5 +71,16 @@
>> #define QSERDES_V8_COM_ADDITIONAL_MISC 0x1b4
>> #define QSERDES_V8_COM_CMN_STATUS 0x2c8
>> #define QSERDES_V8_COM_C_READY_STATUS 0x2f0
>> +#define QSERDES_V8_COM_PLL_IVCO_MODE1 0xf8
>> +#define QSERDES_V8_COM_CMN_IETRIM 0xfc
>> +#define QSERDES_V8_COM_CMN_IPTRIM 0x100
>> +#define QSERDES_V8_COM_VCO_TUNE_CTRL 0x13c
>> +#define QSERDES_V8_COM_ADAPTIVE_ANALOG_CONFIG 0x268
>> +#define QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE0 0x26c
>> +#define QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE0 0x270
>> +#define QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE0 0x274
>> +#define QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE1 0x278
>> +#define QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE1 0x27c
>> +#define QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE1 0x280
>>
>> #endif
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v8.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v8.h
>> new file mode 100644
>> index 000000000000..5f923c3e64ec
>> --- /dev/null
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v8.h
>> @@ -0,0 +1,37 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (c) 2026, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V8_H_
>> +#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V8_H_
>> +
>> +#define QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_TX (0x34)
>> +#define QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_RX (0x38)
>> +#define QSERDES_UFS_V8_TX_LANE_MODE_1 (0x80)
>> +#define QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE2 (0x1BC)
>> +#define QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE4 (0x1C4)
>> +#define QSERDES_UFS_V8_RX_UCDR_SO_GAIN_RATE4 (0x1DC)
>> +#define QSERDES_UFS_V8_RX_EQ_OFFSET_ADAPTOR_CNTRL1 (0x2C8)
>> +#define QSERDES_UFS_V8_RX_UCDR_PI_CONTROLS (0x1E4)
>> +#define QSERDES_UFS_V8_RX_OFFSET_ADAPTOR_CNTRL3 (0x2D0)
>> +#define QSERDES_UFS_V8_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 (0x120)
>> +#define QSERDES_UFS_V8_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 (0xD4)
>> +#define QSERDES_UFS_V8_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 (0xEC)
>> +#define QSERDES_UFS_V8_RX_VGA_CAL_MAN_VAL (0x288)
>> +#define QSERDES_UFS_V8_RX_EQU_ADAPTOR_CNTRL4 (0x2B0)
>> +#define QSERDES_UFS_V8_RX_MODE_RATE_0_1_B4 (0x324)
>> +#define QSERDES_UFS_V8_RX_MODE_RATE4_SA_B7 (0x3B4)
>> +#define QSERDES_UFS_V8_RX_MODE_RATE4_SA_B9 (0x3BC)
>> +#define QSERDES_UFS_V8_RX_MODE_RATE4_SB_B7 (0x3E0)
>> +#define QSERDES_UFS_V8_RX_MODE_RATE4_SB_B9 (0x3E8)
>> +#define QSERDES_UFS_V8_RX_MODE_RATE5_SA_B7 (0x40C)
>> +#define QSERDES_UFS_V8_RX_MODE_RATE5_SA_B9 (0x414)
>> +#define QSERDES_UFS_V8_RX_MODE_RATE5_SB_B7 (0x438)
>> +#define QSERDES_UFS_V8_RX_MODE_RATE5_SB_B9 (0x440)
>> +#define QSERDES_UFS_V8_RX_UCDR_SO_SATURATION (0xF4)
>> +#define QSERDES_UFS_V8_RX_TERM_BW_CTRL0 (0x1AC)
>> +#define QSERDES_UFS_V8_RX_DLL0_FTUNE_CTRL (0x498)
>> +#define QSERDES_UFS_V8_RX_SIGDET_CAL_TRIM (0x4d0)
>> +
>> +#endif
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> index 0f4ad24aa405..d4aca22c181e 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> @@ -29,9 +29,11 @@
>> #include "phy-qcom-qmp-pcs-ufs-v4.h"
>> #include "phy-qcom-qmp-pcs-ufs-v5.h"
>> #include "phy-qcom-qmp-pcs-ufs-v6.h"
>> +#include "phy-qcom-qmp-pcs-ufs-v7.h"
>>
>> #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
>> #include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h"
>> +#include "phy-qcom-qmp-qserdes-txrx-ufs-v8.h"
>>
>> /* QPHY_PCS_READY_STATUS bit */
>> #define PCS_READY BIT(0)
>> @@ -84,6 +86,13 @@ static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
>> [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,
>> };
>>
>> +static const unsigned int ufsphy_v7_regs_layout[QPHY_LAYOUT_SIZE] = {
>> + [QPHY_START_CTRL] = QPHY_V7_PCS_UFS_PHY_START,
>> + [QPHY_PCS_READY_STATUS] = QPHY_V7_PCS_UFS_READY_STATUS,
>> + [QPHY_SW_RESET] = QPHY_V7_PCS_UFS_SW_RESET,
>> + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V7_PCS_UFS_POWER_DOWN_CONTROL,
>> +};
>> +
>> static const struct qmp_phy_init_tbl milos_ufsphy_serdes[] = {
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
>> @@ -1307,6 +1316,11 @@ static const struct regulator_bulk_data sm8750_ufsphy_vreg_l[] = {
>> { .supply = "vdda-pll", .init_load_uA = 18300 },
>> };
>>
>> +static const struct regulator_bulk_data hawi_ufsphy_vreg_l[] = {
>> + { .supply = "vdda-phy", .init_load_uA = 324000 },
>> + { .supply = "vdda-pll", .init_load_uA = 27000 },
>> +};
>> +
>> static const struct qmp_ufs_offsets qmp_ufs_offsets = {
>> .serdes = 0,
>> .pcs = 0xc00,
>> @@ -1325,6 +1339,15 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {
>> .rx2 = 0x1a00,
>> };
>>
>> +static const struct qmp_ufs_offsets qmp_ufs_offsets_v7 = {
>> + .serdes = 0,
>> + .pcs = 0x0400,
>> + .tx = 0x2000,
>> + .rx = 0x2000,
>> + .tx2 = 0x3000,
>> + .rx2 = 0x3000,
>> +};
>> +
>> static const struct qmp_phy_cfg milos_ufsphy_cfg = {
>> .lanes = 2,
>>
>> @@ -1845,6 +1868,119 @@ static const struct qmp_phy_cfg sm8750_ufsphy_cfg = {
>>
>> };
>>
>> +static const struct qmp_phy_init_tbl hawi_ufsphy_serdes[] = {
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0xd9),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x11),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_EN, 0x01),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x60),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_IVCO, 0x1f),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_IVCO_MODE1, 0x1f),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_IETRIM, 0x07),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_IPTRIM, 0x20),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x04),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_CTRL, 0x40),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_ADAPTIVE_ANALOG_CONFIG, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x18),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x14),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x7f),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x4c),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x18),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x14),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x99),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x07),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xbe),
>> + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl hawi_ufsphy_tx[] = {
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_TX_LANE_MODE_1, 0x0c),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_RX, 0x17),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl hawi_ufsphy_rx[] = {
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE2, 0x0c),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE4, 0x0c),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_SO_GAIN_RATE4, 0x04),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_PI_CONTROLS, 0x07),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_VGA_CAL_MAN_VAL, 0x8e),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE_0_1_B4, 0xb8),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SA_B7, 0x66),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SA_B9, 0x1f),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SB_B7, 0x66),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SB_B9, 0x1f),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SA_B7, 0x66),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SA_B9, 0x1f),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SB_B7, 0x66),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SB_B9, 0x1f),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_SO_SATURATION, 0x1f),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_TERM_BW_CTRL0, 0xfa),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_DLL0_FTUNE_CTRL, 0x30),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_SIGDET_CAL_TRIM, 0x77),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl hawi_ufsphy_pcs[] = {
>> + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
>> + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_PCS_CTRL1, 0x42),
>> + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
>> + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
>> + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl hawi_ufsphy_g5_pcs[] = {
>> + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_PLL_CNTL, 0x3b),
>> + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05),
>> + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05),
>> +};
>> +
>> +static const struct qmp_phy_cfg hawi_ufsphy_cfg = {
>> + .lanes = 2,
>> +
>> + .offsets = &qmp_ufs_offsets_v7,
>> + .max_supported_gear = UFS_HS_G5,
>> +
>> + .tbls = {
>> + .serdes = hawi_ufsphy_serdes,
>> + .serdes_num = ARRAY_SIZE(hawi_ufsphy_serdes),
>> + .tx = hawi_ufsphy_tx,
>> + .tx_num = ARRAY_SIZE(hawi_ufsphy_tx),
>> + .rx = hawi_ufsphy_rx,
>> + .rx_num = ARRAY_SIZE(hawi_ufsphy_rx),
>> + .pcs = hawi_ufsphy_pcs,
>> + .pcs_num = ARRAY_SIZE(hawi_ufsphy_pcs),
>> + },
>> +
>> + .tbls_hs_overlay[0] = {
>> + .pcs = hawi_ufsphy_g5_pcs,
>> + .pcs_num = ARRAY_SIZE(hawi_ufsphy_g5_pcs),
>> + .max_gear = UFS_HS_G5,
>> + },
>> +
>> + .vreg_list = hawi_ufsphy_vreg_l,
>> + .num_vregs = ARRAY_SIZE(hawi_ufsphy_vreg_l),
>> + .regs = ufsphy_v7_regs_layout,
>> +};
>> +
>> static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
>> {
>> void __iomem *serdes = qmp->serdes;
>> @@ -2259,6 +2395,9 @@ static int qmp_ufs_probe(struct platform_device *pdev)
>>
>> static const struct of_device_id qmp_ufs_of_match_table[] = {
>> {
>> + .compatible = "qcom,hawi-qmp-ufs-phy",
>> + .data = &hawi_ufsphy_cfg,
>> + }, {
>> .compatible = "qcom,milos-qmp-ufs-phy",
>> .data = &milos_ufsphy_cfg,
>> }, {
>> --
>> 2.34.1
>>
>
Hi Vinod,
Gentle reminder to integrate this patch.
Thanks.
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