[PATCH v5 net-next 1/2] dt-bindings: phy: cadence-torrent: Update property values to support multilink SERDES configuration

[Conor Dooley]

On Wed, Jul 08, 2026 at 02:07:24PM +0530, Gokul Praveen wrote:
> Update the maxItems value of clocks parameter as 3 clocks
> (refclk,pll1_refclk,phy_en_refclk) are supported.
> 
> Update the clock-names parameter to support mutilink SERDES configuration
> as the existing enum configuration of the clock-names parameter does not
> allow both pll1_refclk and phy_en_refclk to be used at the same time,
> hence preventing the support for the configuration  (refclk,pll1_refclk,
> phy_en_refclk), which is neeed for multilink SERDES usecases.
> 
> For multilink SERDES configurations where the links require different
> clock speeds, all 3 clocks(refclk, pll1_refclk and phy_en_refclk)
> are needed.
> 
> For example,considering the USXGMII+SGMII multilink SERDES configuration
> usecase, having only 1 reference clock(refclk) fails because USXGMII
> requires a clock speed of 156.25 Mhz and SGMII protocol requires an
> clock speed of 100 Mhz.
> 
> Since one reference clock(refclk) alone cannot cater to the 2
> different clock speed requirements of these protocols, the second
> input reference clock(pll1_refclk) along with phy_en_refclk
> is also needed.

This binding supports 2 devices and the generic compatible. Do all these
devices have the new refclk?

Thanks,
Conor.

> 
> Signed-off-by: Gokul Praveen <g-praveen at ti.com>
> ---
>  Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> index 9af39b33646a..ac0f625cd76d 100644
> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> @@ -34,7 +34,7 @@ properties:
>  
>    clocks:
>      minItems: 1
> -    maxItems: 2
> +    maxItems: 3
>      description:
>        PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
>        pll1_refclk is optional and used for multi-protocol configurations requiring
> @@ -48,6 +48,7 @@ properties:
>      items:
>        - const: refclk
>        - enum: [ pll1_refclk, phy_en_refclk ]
> +      - const: phy_en_refclk
>  
>    reg:
>      minItems: 1
> -- 
> 2.34.1
> 
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