[PATCH v2 01/12] dt-bindings: phy: Document MT8195 and MT8196 DisplayPort PHYs

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The proposed PHY binding incorrectly models the PHY as a standalone device node with an overlapping `reg` region that conflicts with the existing DP/eDP TX controller.
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--- Patch [1]: [PATCH v2 01/12] dt-bindings: phy: Document MT8195 and MT8196 DisplayPort PHYs ---
commit 697e3d14510b082973bfd257d964015014dae7b9
Author: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

dt-bindings: phy: Document MT8195 and MT8196 DisplayPort PHYs
    
This adds bindings for the DisplayPort and Embedded DisplayPort PHYs found
in the MediaTek MT8195 and MT8196 SoCs. It includes properties for varying
impedance calibrations to optimize the EYE signal pattern.

> diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt8195-dp-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,mt8195-dp-phy.yaml
> new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mediatek,mt8195-dp-phy.yaml
[ ... ]
> +required:
> +  - compatible
> +  - reg
> +  - "#phy-cells"
[ ... ]
> +examples:
> +  - |
> +    phy at 1c500000 {
> +        compatible = "mediatek,mt8195-dp-phy";
> +        reg = <0x1c500000 0x2000>;
[Severity: High]
Will this reg region conflict with the existing DP/eDP TX controller?

The existing MT8195 DP controller node (edp_tx in mt8195.dtsi) already uses
the base address 0x1c500000 for its region, and the monolithic mtk_dp.c
driver requests this entire exclusive region.

If the PHY is modeled as a standalone sibling node with an overlapping memory
bound, it seems the kernel's devm_platform_ioremap_resource will fail with
-EBUSY during driver probe and break the display controller.

Should the PHY instead be modeled as a child node without an absolute reg, or
should these calibration properties be merged directly into the existing
mediatek,dp.yaml controller binding?

> +        #phy-cells = <0>;
> +        nvmem-cells = <&edp_glb_bias_trim>, <&edp_clktx_impsel>,
[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/20260707141931.191172-1-angelogioacchino.delregno@collabora.com?part=1