[PATCH v2 0/3] phy: qcom-qusb2: sort out register layouts

[Dmitry Baryshkov]

IPQ6018 and MSM8996 use the same register layout, however for historical
reasons ipq6018_regs_layout ended up correctly definig TEST1 register at
0x98 (because platforms using that layout didn't use autoresume), while
msm8996_regs_layout used TEST_CTRL offset (0xb8) for the TEST1 layout
entry. Fix handling of the autoresume register and definitions of those
regs layouts.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at oss.qualcomm.com>
---
Changes in v2:
- Reworked the series to enable autoresume on Talos
- Moved autoresume description to the regs layout, it is a property of
  the regs rather than a platform.
- Link to v1: https://patch.msgid.link/20260702-fix-qusb2-v1-0-b5cf55621524@oss.qualcomm.com

To: Vinod Koul <vkoul at kernel.org>
To: Neil Armstrong <neil.armstrong at linaro.org>
To: Krishna Kurapati <krishna.kurapati at oss.qualcomm.com>
To: Dmitry Baryshkov <lumag at kernel.org>
To: Kathiravan T <quic_kathirav at quicinc.com>
To: Baruch Siach <baruch at tkos.co.il>
To: Manu Gautam <mgautam at codeaurora.org>
To: Kishon Vijay Abraham I <kishon at kernel.org>
Cc: linux-arm-msm at vger.kernel.org
Cc: linux-phy at lists.infradead.org
Cc: linux-kernel at vger.kernel.org

---
Dmitry Baryshkov (3):
      phy: qcom-qusb2: enable autoresume on Talos platforms
      phy: qcom-qusb2: correst PHY description for IPQ6018
      phy: qcom-qusb2: describe autoresume bit

 drivers/phy/qualcomm/phy-qcom-qusb2.c | 55 ++++++++++++++++-------------------
 1 file changed, 25 insertions(+), 30 deletions(-)
---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260702-fix-qusb2-3600a65bfcae

Best regards,
--  
With best wishes
Dmitry