[PATCH v4 3/4] phy: qcom-qusb2: Add support for Shikra

[Krishna Kurapati]

On 7/2/2026 7:18 PM, Dmitry Baryshkov wrote:
> On Wed, Jul 01, 2026 at 10:20:50PM +0530, Krishna Kurapati wrote:
>> Add init sequence and phy configuration for Shikra.
>>
>> Signed-off-by: Krishna Kurapati <krishna.kurapati at oss.qualcomm.com>
>> ---
>>   drivers/phy/qualcomm/phy-qcom-qusb2.c | 16 ++++++++++++++++
>>   1 file changed, 16 insertions(+)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> index eb93015be841..ab7437e7b751 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> @@ -381,6 +381,19 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = {
>>   	.autoresume_en	 = BIT(3),
>>   };
>>   
>> +static const struct qusb2_phy_cfg shikra_phy_cfg = {
>> +	.tbl            = qcs615_init_tbl,
>> +	.tbl_num        = ARRAY_SIZE(qcs615_init_tbl),
>> +	.regs           = ipq6018_regs_layout,
> 
> msm8996_regs_layout (otherwise you are programming the wrong register).
> 

ACK. Will send v5 on top of your upcoming v2.

Regards,
Krishna,

>> +
>> +	.has_pll_test	= true,
>> +	.se_clk_scheme_default = true,
>> +	.disable_ctrl   = CLAMP_N_EN | FREEZIO_N | POWER_DOWN,
>> +	.mask_core_ready = PLL_LOCKED,
>> +	.autoresume_en   = BIT(3),
>> +	.update_tune1_with_efuse = false,
>> +};
>> +
>>   static const struct qusb2_phy_cfg sm6115_phy_cfg = {
>>   	.tbl		= sm6115_init_tbl,
>>   	.tbl_num	= ARRAY_SIZE(sm6115_init_tbl),
>> @@ -958,6 +971,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
>>   	}, {
>>   		.compatible	= "qcom,sdm660-qusb2-phy",
>>   		.data		= &sdm660_phy_cfg,
>> +	}, {
>> +		.compatible	= "qcom,shikra-qusb2-phy",
>> +		.data		= &shikra_phy_cfg,
>>   	}, {
>>   		.compatible	= "qcom,sm4250-qusb2-phy",
>>   		.data		= &sm6115_phy_cfg,
>> -- 
>> 2.34.1
>>
>