[PATCH v10 2/5] dt-bindings: phy: Add documentation for Airoha AN7581 USB PHY

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Encoding fixed internal SoC routing in the device tree via the `airoha,usb2-monitor-clk-sel` property.
--

commit 82d75d6a8695c967604982f45c3db95efe45a784
Author: Christian Marangi <ansuelsmth at gmail.com>

dt-bindings: phy: Add documentation for Airoha AN7581 USB PHY

This commit adds device tree binding documentation for the Airoha AN7581
USB PHY. It details properties for configuring the always-supported USB 2.0
mode and the optional USB 3.0 mode, including slew rate calibration and
Serdes configuration.

> diff --git a/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml
> new file mode 100644
> index 0000000000000..f42e3d49a61fd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml
> @@ -0,0 +1,62 @@
[ ... ]
> +  reg:
> +    maxItems: 1
> +
> +  airoha,usb2-monitor-clk-sel:
> +    description: Describe what oscillator across the available 4
> +      should be selected for USB 2.0 Slew Rate calibration.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1, 2, 3]

[Severity: Low]
Since the commit message mentions that each port has only one of the 4 monitor
clocks actually connected in HW, does this property encode a fixed internal
SoC routing rather than a board-specific configuration?

Could the driver deduce the correct clock selection internally (for example,
from the port's register address) instead of requiring a DT property for a
fixed SoC hardware characteristic?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260702093812.15918-1-ansuelsmth@gmail.com?part=2