[PATCH v4 net-next 2/2] arm64: dts: ti: Add PLL1 refclk to J784S4 SoC SERDES node

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The Cadence Torrent PHY multilink configuration will fail on other K3 platforms (e.g., J721S2) due to a missing pll1_refclk property in identical serdes nodes.
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commit cad292e544578dc0fc4b900abd68b229a97dc116
Author: Gokul Praveen <g-praveen at ti.com>

arm64: dts: ti: Add PLL1 refclk to J784S4 SoC SERDES node

This commit adds the PLL1 reference clock to the clocks and clock-names
parameters of the SERDES nodes for the J784S4 and J742S2 SoCs. This resolves
an issue where serdes multilink configurations fail without PLL1.

> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> index c2636e624f18b..e5224bd7f5383 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> @@ -1149,8 +1149,9 @@ serdes0: serdes at 5060000 {
>  			resets = <&serdes_wiz0 0>;
>  			reset-names = "torrent_reset";
>  			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> +				 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
>  				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
> -			clock-names = "refclk", "phy_en_refclk";
> +			clock-names = "refclk",	"pll1_refclk", "phy_en_refclk";

[Severity: High]
This isn't a bug introduced by this patch, but does the same multilink
configuration failure occur on other K3 platforms like J721S2?

Looking at serdes0 in arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi, it lacks
the pll1_refclk property in the clocks array:

    clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
             <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
    clock-names = "refclk", "phy_en_refclk";

When a multilink configuration is requested on these platforms (e.g., PCIe on
lane 0 and SGMII on lane 1), will the phy-cadence-torrent driver fail to
enable the PLL1 reference clock?

Could this cause essential peripheral initialization to fail when the
PHY is unable to lock PLL1?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260701142457.81874-1-g-praveen@ti.com?part=2