[PATCH v2 2/5] dt-bindings: PCI: qcom,shikra-pcie: Document the Shikra PCIe Controller

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The binding schema fails to structurally enforce the maximum link speed limitation of the hardware.
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commit 97340dc07e6512ba3b927b4bb3ca4453e76e80c8
Author: Sushrut Shree Trivedi <sushrut.trivedi at oss.qualcomm.com>

dt-bindings: PCI: qcom,shikra-pcie: Document the Shikra PCIe Controller

Add a dedicated schema for the PCIe controller found on the Shikra platform.
The controller supports up to PCIe Gen3, but the PHY is limited to Gen2, so
the max link speed is restricted to avoid link-up failures.

> diff --git a/Documentation/devicetree/bindings/pci/qcom,shikra-pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,shikra-pcie.yaml
> new file mode 100644
> index 0000000000000..73b8ec722f2a0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/qcom,shikra-pcie.yaml
[ ... ]
> +description:
> +  Qualcomm Shikra SoC PCIe Root Complex is based on
> +  the Synopsys DesignWare PCIe IP.
> +
> +properties:
> +  compatible:
> +    const: qcom,shikra-pcie

[Severity: Medium]
Since the commit message notes the PHY is only capable of Gen2 and the max
link speed must be limited to Gen2, should we structurally enforce this limit
in the properties block?

Without specifying max-link-speed: maximum: 2 (or enum: [1, 2]) here, the
schema inherits the default generic limit (maximum 5), allowing invalid
device trees with a max-link-speed greater than 2 to silently pass
dt_binding_check.

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Sashiko AI review · https://sashiko.dev/#/patchset/20260831-shikra-upstream-v2-0-406661d75afa@oss.qualcomm.com?part=2