[PATCH v3 01/12] dt-bindings: phy: qcom,ipq5332-uniphy-pcie: Change to PCIe/USB3 combo PHY

[George Moussalem]

On 8/28/26 14:09, Krzysztof Kozlowski wrote:
> On Tue, Aug 25, 2026 at 04:37:18PM +0400, George Moussalem wrote:
>> This PHY is a PCIE/USB3 multi-purpose PHY. Initial support was added for
>> PCIe only, so rename the binding and add support for USB3 PHY mode.
>>
>> The PCIe and USB physical pads are muxed and selection is done via a
>> control register in TCSR. Add a new property to the binding to enable
>> switching the default PCIe mux selection to USB3 mode.
>>
>> In addition, USB3 mode requires a 5V supply, so add a vdd-supply
>> property for it.
>>
>> Signed-off-by: George Moussalem <george.moussalem at outlook.com>
>> ---
>>  .../bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 109 ----------------
>>  .../phy/qcom,ipq5332-uniphy-pcie-usb3-phy.yaml     | 141 +++++++++++++++++++++
>>  include/dt-bindings/phy/phy-qcom-qmp.h             |   4 +
>>  3 files changed, 145 insertions(+), 109 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
>> deleted file mode 100644
>> index 6e9df81441e9..000000000000
> 
> Please do not rename the binding. Old name was correct. New one is not,
> otherwise please point me to the compatible like that.

I thought we had come to the conclusion it's the same device in the
discussion in v2:
https://lore.kernel.org/all/gn43qixdtbq5iyfqvzibdtx4lmwpkt2ieahr7oqsxxjfpldb6d@xbxhbdrq4e6b/

I've split up this series into 3 as in the cover letter:
1. Flatten USB Controller Nodes on IPQ SoCs
   link:
https://lore.kernel.org/r/20260825-ipq-flatten-usb-v1-0-5c1f3170bbe9@outlook.com
2. Enable USB3 for Qualcomm IPQ5018 (this patch series)
3. Enable USB3 for Qualcomm IPQ5332 (to be submitted)

Since 2 is dependent on 1, I thought I'd wait for the feedback first on
1, then submit 3 which is dependent on 2.

But eventually, the IPQ5332 combo PHY looks like:

	pcie0_phy: phy at 4b0000 {
		compatible = "qcom,ipq5332-uniphy-pcie-usb3-phy";
		reg = <0x004b0000 0x800>;
		clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
			 <&gcc GCC_PCIE3X1_PHY_AHB_CLK>,
			 <&gcc GCC_USB0_PIPE_CLK>,
			 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
		clock-names = "pcie-pipe",
			      "pcie-ahb",
			      "usb3-pipe",
			      "usb3-cfg-ahb";

		resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
			 <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
			 <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>,
			 <&gcc GCC_USB0_PHY_BCR>;
		reset-names = "pcie-phy",
			      "pcie-ahb",
			      "pcie-cfg",
			      "usb3-phy";

		#clock-cells = <1>;
		#phy-cells = <1>;

		num-lanes = <1>;

		status = "disabled";
	};

I have the patches ready. Let me know if you'd like them submitted.
The idea was to prepare the binding for both IPQ5018 USB3 and IPQ5332
PCIe/USB3, hence the rename from pcie -> pcie-usb3

> 
> Best regards,
> Krzysztof
> 

Best regards,
George