[PATCH v3 2/4] phy: qualcomm: qmp-combo: Update DP PHY common init tables
Abel Vesa
abel.vesa at oss.qualcomm.com
Fri Aug 28 03:19:03 PDT 2026
On 26-08-28 15:13:14, Nabige Aala wrote:
> From: Ritesh Kumar <ritesh.kumar at oss.qualcomm.com>
>
> Update common DP PHY serdes and TX initialization tables with
> corrected PLL control values (MODE0 instead of MODE1), updated
> SSC step size, reset control, and various TX lane configuration
> parameters including emphasis levels and driver enable settings.
>
> Signed-off-by: Ritesh Kumar <ritesh.kumar at oss.qualcomm.com>
> Signed-off-by: Mahadevan P <mahadevan.p at oss.qualcomm.com>
> Signed-off-by: Nabige Aala <nabige.aala at oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa at oss.qualcomm.com>
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