[PATCH v3 1/4] phy: qualcomm: qmp-combo: Add DP COM v8 header and fix register layout

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

New issues:
- [Low] Incomplete Implementation: The patch introduces DP V8 COM specific macros but fails to use them for all applicable COM registers in `qmp_v8_n3_usb43dpphy_regs_layout`.

Pre-existing issues:
- [High] Incomplete Register Layout Fix: `qmp_v8_usb3phy_regs_layout` incorrectly uses USB COM offsets for DP polling registers.
--

commit dc18b235eac5c4be7adfceadd9f5cb3a146a62c0
Author: Ritesh Kumar <ritesh.kumar at oss.qualcomm.com>

phy: qualcomm: qmp-combo: Add DP COM v8 header and fix register layout

Add the new DP-specific QSERDES COM v8 header file and update the
register layout to use DP-specific status register offsets for
C_READY_STATUS and CMN_STATUS registers.

> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index c39ced168d035..4d31637f1dce6 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c

[ ... ]

> @@ -318,8 +319,8 @@ static const unsigned int qmp_v8_n3_usb43dpphy_regs_layout[QPHY_LAYOUT_SIZE] = {
>  	[QPHY_DP_AON_TOGGLE_ENABLE]		= QPHY_V8_PCS_AON_DP_AON_TOGGLE_ENABLE,
>  
>  	[QPHY_COM_RESETSM_CNTRL]		= QSERDES_V8_COM_RESETSM_CNTRL,
> -	[QPHY_COM_C_READY_STATUS]		= QSERDES_V8_COM_C_READY_STATUS,
> -	[QPHY_COM_CMN_STATUS]			= QSERDES_V8_COM_CMN_STATUS,
> +	[QPHY_COM_C_READY_STATUS]		= DP_QSERDES_V8_COM_C_READY_STATUS,
> +	[QPHY_COM_CMN_STATUS]			= DP_QSERDES_V8_COM_CMN_STATUS,
>  	[QPHY_COM_BIAS_EN_CLKBUFLR_EN]	= QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN,

[Severity: Low]
Should QPHY_COM_RESETSM_CNTRL and QPHY_COM_BIAS_EN_CLKBUFLR_EN also be
updated to use the new DP_QSERDES_V8_COM_* macros?

Since the patch aims to decouple DP V8 COM macros from USB V8 COM macros,
leaving these keys mapped to QSERDES_V8_COM_* instead of the new
DP_QSERDES_V8_COM_* variants seems to skip part of the semantic separation.

[Severity: High]
This is a pre-existing issue, but I noticed another layout that might have
a similar problem with DP polling registers.

Looking at qmp_v8_usb3phy_regs_layout[] earlier in this file:

drivers/phy/qualcomm/phy-qcom-qmp-combo.c:qmp_v8_usb3phy_regs_layout[] {
    ...
    [QPHY_COM_C_READY_STATUS]       = QSERDES_V8_COM_C_READY_STATUS,
    [QPHY_COM_CMN_STATUS]           = QSERDES_V8_COM_CMN_STATUS,
    ...
}

This layout is used by the sm8750_usb3dpphy_cfg combo PHY configuration.

During DP initialization, qmp_combo_configure_dp_phy_common() polls
QPHY_COM_C_READY_STATUS and QPHY_COM_CMN_STATUS on the dp_serdes block:

    readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], ...);

Since this layout maps these to the USB V8 offsets (0x2f0 and 0x2c8) rather
than the DP V8 offsets (0x33c and 0x314) or DP V6 offsets (0x1f8 and 0x1d0),
will this cause DP initialization to read incorrect memory and time out on
sm8750 devices?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260828-glymur-phy-v3-v3-0-8e73ce7c4636@oss.qualcomm.com?part=1