[PATCH v2 4/4] phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support

[sashiko-bot at kernel.org]

> Add support for the Nord Gen5x16 bifurcated QMP PCIe PHY.
> 
> Nord has a single PCIe PHY block split into four ports which can be
> used in multiple lane configurations: x16, x8+x8, x8+x4+x4 and
> x8+x4+x2+x2. The active topology is selected through the link mode
> configuration register, and the driver exposes the corresponding PHY
> instances based on that mode.
> 
> Unlike Glymur, where the PHY is initialized by firmware, Nord requires
> Linux to program the PHY registers. Add the PLL, TXRXZ, PCS and PCS
> lane initialization tables, along with the required power-up,
> power-down and soft-reset sequencing.
> 
> Add per-port and grouped PHY configurations for all supported Nord
> lane modes. Also add support for regular PHY resets in addition to the
> NOCSR resets, and handle the shared PHY power domain by attaching it
> once at the multi-PHY level and reusing it across segment groups. The
> GDSC init is now done using the device created for the PHY itself
> (devm_phy_create()), rather than the parent multi-PHY platform device.
> 
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru at oss.qualcomm.com>

Sashiko has reviewed this patch and found no issues. It looks great!

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Sashiko AI review · https://sashiko.dev/#/patchset/20260828-nord-v2-0-18bf59d19d6f@oss.qualcomm.com?part=4