[PATCH v2 1/2] dt-bindings: phy: airoha: Document support for AN7583 Gen3 PCIe PHY

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Incorrect memory region size in the device tree example (0xfff instead of 0x1000).
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commit 41aa642fd5dfb10ea2b50d62af99f95cc040fb55
Author: Christian Marangi <ansuelsmth at gmail.com>

dt-bindings: phy: airoha: Document support for AN7583 Gen3 PCIe PHY

Document support for AN7583 PCIe PHY used to make the Gen3 PCIe port
work. Add the required register to configure the PCIe PHY and provide an
example for it.

> diff --git a/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen3-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen3-phy.yaml
> new file mode 100644
> index 0000000000000..07bb20152c0a7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen3-phy.yaml

[ ... ]

> +examples:
> +  - |
> +    #include <dt-bindings/phy/phy.h>
> +
> +    phy at 1fc7f000 {
> +        compatible = "airoha,an7583-pcie-gen3-phy";
> +        reg = <0x1fc7f000 0xfff>,
> +              <0x1fc7e000 0xfff>,

[Severity: Low]
Are these memory region sizes off-by-one?

Since the base addresses (0x1fc7e000 and 0x1fc7f000) are exactly 4KB (0x1000)
apart, a size of 0xfff (4095 bytes) mathematically leaves the last byte of the
4KB block unmapped.

While ioremap rounds up to the page size meaning there is likely no functional
failure in practice, should this specify 0x1000 instead to prevent propagating
off-by-one size errors to consumers of this example?

> +              <0x1fc30044 0x4>,
> +              <0x1fc35030 0x4>;
> +        reg-names = "g3-ana", "g3-pma",
> +                    "xr-dtime", "rx-aeq";
> +
> +        phys = <&pcie1_phy PHY_TYPE_PCIE>;
> +
> +        #phy-cells = <0>;
> +    };

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Sashiko AI review · https://sashiko.dev/#/patchset/20260827122127.18874-1-ansuelsmth@gmail.com?part=1