[PATCH v11 08/12] clk: zte: Add zx PLL support infrastructure

[sashiko-bot at kernel.org]

> This patch adds code to decode and program PLL settings on ZTE's
> zx297520v3 SoC. The PLLs on this SoC are usually programmed to static
> values by the boot loader. The only situation where .set_rate matters is
> dpll, which is not programmed in some cases. The bootloader always sets
> fixed rates though: 624 MHz for mpll, 200 for gpll, 480 for upll.
> 
> Parsing the bootloader-programmed values allows the clock driver to fill
> the clock tree with appropriately clocked parent clocks instead of
> registering fixed clocks with hardcoded rates.
> 
> I only tested the code on zx297520v3. From looking at the hardcoded PLL
> values in the old zx296702 / zx296718 code I believe that these PLLs use
> the same encoding, so the code added by this patch should be reusable
> and the file has a relatively generic name pll-zx.c.
> 
> Reviewed-by: Brian Masney <bmasney at redhat.com>
> Signed-off-by: Stefan Dösinger <stefandoesinger at gmail.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260826-zx29clk-v11-0-f8ad59c6426c@gmail.com?part=8