[PATCH 1/4] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding

[Krzysztof Kozlowski]

On 25/08/2026 05:40, Krishna Chaitanya Chundru wrote:
> Document the PCIe PHY found on the Qualcomm Nord platform.
> 
> Nord has a Gen5-capable QMP PCIe PHY that can operate in multiple
> lane configurations using four PHY segments (A/B/C/D). The active
> topology is selected by firmware through a TCSR configuration
> register and may be configured as x16, x8+x8, x8+x4+x4, or
> x8+x4+x2+x2.
> 
> The binding describes the register regions, clocks, resets, power
> domains, regulators, PHY provider interface, clock provider interface,
> and the qcom,link-mode property used by the driver to discover the
> active lane configuration programmed by firmware.
> 
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru at oss.qualcomm.com>
> ---
>  .../bindings/phy/qcom,nord-qmp-pcie-phy.yaml       | 276 +++++++++++++++++++++
>  1 file changed, 276 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,nord-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-pcie-phy.yaml
> new file mode 100644
> index 000000000000..3575e99dadfd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-pcie-phy.yaml
> @@ -0,0 +1,276 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,nord-qmp-pcie-phy.yaml#

Filename should match compatible.

...

> +            #clock-cells = <1>;
> +            clock-output-names = "pcie_a_pipe_clk",
> +                                 "pcie_b_pipe_clk",
> +                                 "pcie_c_pipe_clk",
> +                                 "pcie_d_pipe_clk";
> +
> +            #phy-cells = <1>;
> +            status = "disabled";

So your code was never tested. Drop. Please read carefully writing
bindings/schema, DTS101 or internal guideline.


Best regards,
Krzysztof