[PATCH 4/5] phy: qcom: snps-femto-v2: Move PHY init registers to config tables
Varadarajan Narayanan
varadarajan.narayanan at oss.qualcomm.com
Sun Aug 23 23:37:44 PDT 2026
The driver currently programs the common PHY register sequence directly in
qcom_snps_hsphy_init(), with the fixed register writes split around the
override parameter handling. This makes it hard to support SoCs that need a
different sequence or different values.
Move the fixed pre- and post-override register programming into per-
compatible configuration tables, and keep the 7 nm override parameters in
the same match-data structure. This allows the driver to share the common
sequence while adding SoC-specific sequences for future platforms such as
IPQ9650.
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan at oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 120 ++++++++++++++++----------
1 file changed, 74 insertions(+), 46 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
index 980ad1fb1e2e..5ffbe1a77dd4 100644
--- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
+++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
@@ -104,6 +104,18 @@ struct phy_override_seq {
u8 mask;
};
+struct phy_reg_config {
+ u32 offset;
+ u32 mask;
+ u32 val;
+};
+
+struct phy_config_data {
+ const struct phy_reg_config *pre;
+ const struct override_param_map *override;
+ const struct phy_reg_config *post;
+};
+
#define NUM_HSPHY_TUNING_PARAMS (9)
/**
@@ -383,13 +395,42 @@ static const struct override_param_map sc7280_snps_7nm_phy[] = {
{},
};
+static const struct phy_reg_config hs_5nm_phy_pre[] = {
+ { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, UTMI_PHY_CMN_CTRL_OVERRIDE_EN },
+ { USB2_PHY_USB_PHY_UTMI_CTRL5, POR, POR },
+ { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, FSEL_MASK, 0 },
+ { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, PLLBTUNE, PLLBTUNE },
+ { USB2_PHY_USB_PHY_REFCLK_CTRL, REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK },
+ { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, VBUSVLDEXTSEL0, VBUSVLDEXTSEL0 },
+ { USB2_PHY_USB_PHY_HS_PHY_CTRL1, VBUSVLDEXT0, VBUSVLDEXT0 },
+ { UINT_MAX, 0, 0 },
+};
+
+static const struct phy_reg_config hs_5nm_phy_post[] = {
+ { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, VREGBYPASS, VREGBYPASS },
+ { USB2_PHY_USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL | USB2_SUSPEND_N,
+ USB2_SUSPEND_N_SEL | USB2_SUSPEND_N },
+ { USB2_PHY_USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM },
+ { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ, 0 },
+ { USB2_PHY_USB_PHY_UTMI_CTRL5, POR, 0 },
+ { USB2_PHY_USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 0 },
+ { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0 },
+ { UINT_MAX, 0, 0 },
+};
+
static int qcom_snps_hsphy_init(struct phy *phy)
{
struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
+ const struct phy_config_data *data;
+ const struct phy_reg_config *tmp;
int ret, i;
dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__);
+ data = of_device_get_match_data(hsphy->dev);
+ if (!data)
+ return -ENODEV;
+
ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
if (ret)
return ret;
@@ -414,24 +455,8 @@ static int qcom_snps_hsphy_init(struct phy *phy)
goto disable_clks;
}
- qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
- UTMI_PHY_CMN_CTRL_OVERRIDE_EN,
- UTMI_PHY_CMN_CTRL_OVERRIDE_EN);
- qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
- POR, POR);
- qcom_snps_hsphy_write_mask(hsphy->base,
- USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,
- FSEL_MASK, 0);
- qcom_snps_hsphy_write_mask(hsphy->base,
- USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
- PLLBTUNE, PLLBTUNE);
- qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL,
- REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK);
- qcom_snps_hsphy_write_mask(hsphy->base,
- USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
- VBUSVLDEXTSEL0, VBUSVLDEXTSEL0);
- qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1,
- VBUSVLDEXT0, VBUSVLDEXT0);
+ for (tmp = data->pre; tmp->offset != UINT_MAX; tmp++)
+ qcom_snps_hsphy_write_mask(hsphy->base, tmp->offset, tmp->mask, tmp->val);
for (i = 0; i < ARRAY_SIZE(hsphy->update_seq_cfg); i++) {
if (hsphy->update_seq_cfg[i].need_update)
@@ -441,28 +466,8 @@ static int qcom_snps_hsphy_init(struct phy *phy)
hsphy->update_seq_cfg[i].value);
}
- qcom_snps_hsphy_write_mask(hsphy->base,
- USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2,
- VREGBYPASS, VREGBYPASS);
-
- qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
- USB2_SUSPEND_N_SEL | USB2_SUSPEND_N,
- USB2_SUSPEND_N_SEL | USB2_SUSPEND_N);
-
- qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0,
- SLEEPM, SLEEPM);
-
- qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,
- SIDDQ, 0);
-
- qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
- POR, 0);
-
- qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
- USB2_SUSPEND_N_SEL, 0);
-
- qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
- UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0);
+ for (tmp = data->post; tmp->offset != UINT_MAX; tmp++)
+ qcom_snps_hsphy_write_mask(hsphy->base, tmp->offset, tmp->mask, tmp->val);
hsphy->phy_initialized = true;
@@ -495,14 +500,34 @@ static const struct phy_ops qcom_snps_hsphy_gen_ops = {
.owner = THIS_MODULE,
};
+static const struct phy_config_data hs_5nm_phy = {
+ .pre = hs_5nm_phy_pre,
+ .post = hs_5nm_phy_post,
+};
+
+static const struct phy_config_data hs_7nm_phy = {
+ .pre = hs_5nm_phy_pre,
+ .override = sc7280_snps_7nm_phy,
+ .post = hs_5nm_phy_post,
+};
+
static const struct of_device_id qcom_snps_hsphy_of_match_table[] = {
- { .compatible = "qcom,sm8150-usb-hs-phy", },
- { .compatible = "qcom,usb-snps-hs-5nm-phy", },
+ {
+ .compatible = "qcom,sm8150-usb-hs-phy",
+ .data = &hs_5nm_phy,
+ },
+ {
+ .compatible = "qcom,usb-snps-hs-5nm-phy",
+ .data = &hs_5nm_phy,
+ },
{
.compatible = "qcom,usb-snps-hs-7nm-phy",
- .data = &sc7280_snps_7nm_phy,
+ .data = &hs_7nm_phy,
+ },
+ {
+ .compatible = "qcom,usb-snps-femto-v2-phy",
+ .data = &hs_5nm_phy,
},
- { .compatible = "qcom,usb-snps-femto-v2-phy", },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_of_match_table);
@@ -541,11 +566,14 @@ static void qcom_snps_hsphy_read_override_param_seq(struct device *dev)
s32 val;
int ret, i;
struct qcom_snps_hsphy *hsphy;
- const struct override_param_map *cfg = of_device_get_match_data(dev);
+ const struct phy_config_data *data = of_device_get_match_data(dev);
+ const struct override_param_map *cfg;
- if (!cfg)
+ if (!data || !data->override)
return;
+ cfg = data->override;
+
hsphy = dev_get_drvdata(dev);
for (i = 0; cfg[i].prop_name != NULL; i++) {
--
2.34.1
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