[PATCH RFC 4/4] arm64: dts: freescale: Add chargebyte Charge Control Y

[Stefan Wahren]

Hi Parthiban,
hi Selvamani,
hi Ciprian,

Am 18.08.26 um 11:31 schrieb sashiko-bot at kernel.org:
> Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
> - [Medium] The LAN8651 ethernet device is missing its hardware reset configuration, leaving the `X_nRST_LAN` pin unmanaged.
> - [Medium] The SD card slot power/reset pin (`SD2_nRESET`) is named in `gpio-line-names` but is not associated with any regulator or reset control.
> - [Low] The GPIO label `X_LAN_nCS` is incorrectly placed at index 0 of `&gpio2`'s `gpio-line-names` array, but the `lan8651` chip select is actually wired to index 8.
> - [Low] The `ti,leds-polarity` property used in both Ethernet PHY nodes is undocumented, invalid, and will cause `dtbs_check` validation errors.
> --
>
> --- Patch [4]: [PATCH RFC 4/4] arm64: dts: freescale: Add chargebyte Charge Control Y ---
> commit a177a5e0acba62156876ea6dc84457789786bfb8
> Author: Stefan Wahren <wahrenst at gmx.net>
...
> +/* MCS Ethernet SPI */
> +&lpspi3 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_lpspi3>;
> +	num-cs = <1>;
> +	cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
> +	status = "okay";
> +
> +	lan8651: ethernet at 0 {
> +		compatible = "microchip,lan8651", "microchip,lan8650";
> +		reg = <0>;
> +		interrupt-parent = <&gpio2>;
> +		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
> +		spi-max-frequency = <25000000>;
> +
> +		nvmem-cells = <&eth2_mac_address 0>;
> +		nvmem-cell-names = "mac-address";
> +	};
> +};
> [Severity: Medium]
> The pin X_nRST_LAN is labeled in the gpio1 node, but this ethernet node
> doesn't seem to configure a reset mechanism. Does the LAN8651 need a reset
> control or gpio-hog to ensure the pin is driven and not left floating?
according to the current DT binding of LAN8651 there is no reset 
control, but the chip has a reset line and its wired on our board.

Are there any plans to implement reset control for OA TC6 or LAN8651?

Best regards