[PATCH v2 01/14] dt-bindings: phy: Document the Qualcomm IPQ5332 UNIPHY USB Super-speed PHY

[George Moussalem via B4 Relay]

From: Praveenkumar I <quic_ipkumar at quicinc.com>

Document the Qualcomm USB3 22ull UNIPHY present in the IPQ5018 and
IPQ5332 SoCs.

Signed-off-by: Praveenkumar I <quic_ipkumar at quicinc.com>
Signed-off-by: George Moussalem <george.moussalem at outlook.com>
---
 .../phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml        | 111 +++++++++++++++++++++
 1 file changed, 111 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml
new file mode 100644
index 000000000000..cc9eccac51dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml
@@ -0,0 +1,111 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm UNIPHY USB Super-Speed 22ull PHY
+
+maintainers:
+  - Praveenkumar I <quic_ipkumar at quicinc.com>
+  - Varadarajan Narayanan <quic_varada at quicinc.com>
+
+description:
+  USB Super-Speed UNIPHY found in Qualcomm IPQ5018 & IPQ5332 SoCs.
+
+properties:
+  compatible:
+    enum:
+      - qcom,ipq5018-uniphy-usb-ss-phy
+      - qcom,ipq5332-uniphy-usb-ss-phy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 2
+    maxItems: 3
+
+  resets:
+    maxItems: 1
+
+  vdd-supply:
+    description:
+      Phandle to 5V regulator supply to PHY digital circuit.
+
+  qcom,phy-usb-mux-sel:
+    description: |
+      Mux selection for USB PHY. The USB3 and PCIe PHY pads are muxed and the
+      mux selection is done via a register in TCSR syscon.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle of TCSR syscon
+          - description: offset of PHY mux selection register
+
+  "#clock-cells":
+    const: 0
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+  - vdd-supply
+  - qcom,phy-usb-mux-sel
+  - "#clock-cells"
+  - "#phy-cells"
+
+additionalProperties: false
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,ipq5018-uniphy-usb-ss-phy
+    then:
+      properties:
+        clocks:
+          items:
+            - description: USB3 PHY CFG AHB clock
+            - description: USB3 pipe clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,ipq5332-uniphy-usb-ss-phy
+    then:
+      properties:
+        clocks:
+          items:
+            - description: Shared PCIe/USB3 PHY AHB clock
+            - description: USB3 PHY CFG AHB clock
+            - description: USB3 pipe clock
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
+
+    phy at 4b0000 {
+        compatible = "qcom,ipq5332-uniphy-usb-ss-phy";
+        reg = <0x4b0000 0x800>;
+
+        clocks = <&gcc GCC_PCIE3X1_PHY_AHB_CLK>,
+                 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+                 <&gcc GCC_USB0_PIPE_CLK>;
+        resets = <&gcc GCC_USB0_PHY_BCR>;
+
+        #clock-cells = <0>;
+        #phy-cells = <0>;
+
+        qcom,phy-usb-mux-sel = <&tcsr 0x10540>;
+
+        vdd-supply = <&regulator_fixed_5p0>;
+    };

-- 
2.53.0