[PATCH 4/6] phy: qcom-qmp: pcs-pcie: Add v8 register offsets

[Dmitry Baryshkov]

On Wed, Sep 24, 2025 at 04:33:20PM -0700, Jingyi Wang wrote:
> From: Qiang Yu <qiang.yu at oss.qualcomm.com>
> 
> Kaanapali SoC uses QMP phy with version v8 for PCIe Gen3 x2. Add the new
> PCS PCIE specific offsets in a dedicated header file.
> 
> Signed-off-by: Qiang Yu <qiang.yu at oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang at oss.qualcomm.com>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v8.h | 35 +++++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v8.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v8.h
> new file mode 100644
> index 000000000000..5d630e5123a5
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v8.h
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. All rights reserved.
> + */
> +
> +#ifndef QCOM_PHY_QMP_PCS_PCIE_V8_H_
> +#define QCOM_PHY_QMP_PCS_PCIE_V8_H_
> +
> +/* Only for QMP V8 PHY - PCIE PCS registers */
> +
> +#define QPHY_PCIE_V8_PCS_POWER_STATE_CONFIG2		0x00c
> +#define QPHY_PCIE_V8_PCS_TX_RX_CONFIG		0x018
> +#define QPHY_PCIE_V8_PCS_ENDPOINT_REFCLK_DRIVE	0x01c
> +#define QPHY_PCIE_V8_PCS_OSC_DTCT_ACTIONS		0x090
> +#define QPHY_PCIE_V8_PCS_EQ_CONFIG1			0x0a0
> +#define QPHY_PCIE_V8_PCS_G3_RXEQEVAL_TIME		0x0f0
> +#define QPHY_PCIE_V8_PCS_G4_RXEQEVAL_TIME		0x0f4
> +#define QPHY_PCIE_V8_PCS_G4_EQ_CONFIG5		0x108
> +#define QPHY_PCIE_V8_PCS_G4_PRE_GAIN			0x15c
> +#define QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG1	0x17c
> +#define QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG3	0x184
> +#define QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG5	0x18c
> +#define QPHY_PCIE_V8_PCS_G3_FOM_EQ_CONFIG5		0x1ac
> +#define QPHY_PCIE_V8_PCS_G4_FOM_EQ_CONFIG5		0x1c0
> +#define QPHY_PCIE_V8_PCS_POWER_STATE_CONFIG6			0x1d0
> +
> +#define QPHY_PCIE_V8_PCS_G12S1_TXDEEMPH_M6DB			0x170
> +#define QPHY_PCIE_V8_PCS_G3S2_PRE_GAIN			0x178

Please keep them sorted.

> +#define QPHY_PCIE_V8_PCS_RX_SIGDET_LVL			0x190
> +#define QPHY_PCIE_V8_PCS_ELECIDLE_DLY_SEL			0x1b8
> +#define QPHY_PCIE_V8_PCS_PCS_TX_RX_CONFIG1			0x1dc
> +#define QPHY_PCIE_V8_PCS_PCS_TX_RX_CONFIG2			0x1e0
> +#define QPHY_PCIE_V8_PCS_EQ_CONFIG4			0x1f8
> +#define QPHY_PCIE_V8_PCS_EQ_CONFIG5			0x1fc
> +#endif
> 
> -- 
> 2.25.1
> 

-- 
With best wishes
Dmitry