[PATCH v2 phy 15/16] phy: lynx-28g: truly power the lanes up or down

[Josua Mayer]

Am 23.09.25 um 21:44 schrieb Vladimir Oltean:
> The current procedure for power_off() and power_on() is the same as the
> one used for major lane reconfiguration, aka halting.
>
> But one would expect that a powered off lane causes the CDR (clock and
> data recovery) loop of the link partner to lose lock onto its RX stream
> (which suggests there are no longer any bit transitions => the channel
> is inactive). However, this does not take place (the CDR lock is still
> there), so a halted lane is still active.
>
> Implement the procedure mentioned in the block guide for powering down
> a lane, and then back on.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean at nxp.com>
> ---
> v1->v2: slight commit message reword
>
>  drivers/phy/freescale/phy-fsl-lynx-28g.c | 78 ++++++++++++++++++------
>  1 file changed, 60 insertions(+), 18 deletions(-)
cut
> +static int lynx_28g_power_off(struct phy *phy)
> +{
> +	struct lynx_28g_lane *lane = phy_get_drvdata(phy);
> +	u32 trstctl, rrstctl;
> +
> +	if (!lane->powered_up)
> +		return 0;
> +
> +	/* Issue a stop request */
> +	lynx_28g_lane_rmw(lane, LNaTRSTCTL, LNaTRSTCTL_STP_REQ,
> +			  LNaTRSTCTL_STP_REQ);
> +	lynx_28g_lane_rmw(lane, LNaRRSTCTL, LNaRRSTCTL_STP_REQ,
> +			  LNaRRSTCTL_STP_REQ);
> +
> +	/* Wait until the stop process is complete */
> +	do {
> +		trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
> +		rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
> +	} while ((trstctl & LNaTRSTCTL_STP_REQ) ||
> +		 (rrstctl & LNaRRSTCTL_STP_REQ));

Unbounded loop, perhaps use timeout.

This can fail on unbalanced calls as you discovered,
but also e.g. when a pll is unstable.

See below for when this came up previously:

https://lore.kernel.org/all/20240218-lynx28g-infinite-loop-v1-1-59cc5cef8367@solid-run.com/