[PATCH v3 0/3] phy: qcom: edp: Add missing ref clock to x1e80100

[Xilin Wu]

On 9/19/2025 7:54 PM, Abel Vesa wrote:
> On 25-09-19 19:06:36, Xilin Wu wrote:
>> On 9/9/2025 3:33 PM, Abel Vesa wrote:
>>> According to documentation, the DP PHY on x1e80100 has another clock
>>> called ref.
>>>
>>> The current X Elite devices supported upstream work fine without this
>>> clock, because the boot firmware leaves this clock enabled. But we should
>>> not rely on that. Also, when it comes to power management, this clock
>>> needs to be also disabled on suspend. So even though this change breaks
>>> the ABI, it is needed in order to make we disable this clock on runtime
>>> PM, when that is going to be enabled in the driver.
>>>
>>> So rework the driver to allow different number of clocks, fix the
>>> dt-bindings schema and add the clock to the DT node as well.
>>>
>>> Signed-off-by: Abel Vesa <abel.vesa at linaro.org>
>>> ---
>>> Changes in v3:
>>> - Use dev_err_probe() on clocks parsing failure.
>>> - Explain why the ABI break is necessary.
>>> - Drop the extra 'clk' suffix from the clock name. So ref instead of
>>>     refclk.
>>> - Link to v2: https://lore.kernel.org/r/20250903-phy-qcom-edp-add-missing-refclk-v2-0-d88c1b0cdc1b@linaro.org
>>>
>>> Changes in v2:
>>> - Fix schema by adding the minItems, as suggested by Krzysztof.
>>> - Use devm_clk_bulk_get_all, as suggested by Konrad.
>>> - Rephrase the commit messages to reflect the flexible number of clocks.
>>> - Link to v1: https://lore.kernel.org/r/20250730-phy-qcom-edp-add-missing-refclk-v1-0-6f78afeadbcf@linaro.org
>>>
>>> ---
>>> Abel Vesa (3):
>>>         dt-bindings: phy: qcom-edp: Add missing clock for X Elite
>>>         phy: qcom: edp: Make the number of clocks flexible
>>>         arm64: dts: qcom: Add missing TCSR ref clock to the DP PHYs
>>>
>>>    .../devicetree/bindings/phy/qcom,edp-phy.yaml      | 28 +++++++++++++++++++++-
>>>    arch/arm64/boot/dts/qcom/x1e80100.dtsi             | 12 ++++++----
>>>    drivers/phy/qualcomm/phy-qcom-edp.c                | 16 ++++++-------
>>>    3 files changed, 43 insertions(+), 13 deletions(-)
>>> ---
>>> base-commit: 65dd046ef55861190ecde44c6d9fcde54b9fb77d
>>> change-id: 20250730-phy-qcom-edp-add-missing-refclk-5ab82828f8e7
>>>
>>> Best regards,
>>
>> Hi,
>>
>> I'm observing what looks like a related clock failure on sc8280xp when
>> booting without a monitor connected to a DP-to-HDMI bridge on mdss0_dp2.
> 
> Am I to understand that this is triggered by this patchset ?
> 
Sorry, it's not indeed. I just saw this patchset and wondered if it can 
fix the issue on sc8280xp. Just now I tried adding the missing 
GCC_EDP2_PHY_CLKREF_EN to DT and gcc driver, but it didn't fix the issue. :(

> I don't see how though.
> 
>>
>> Do you think sc8280xp might require a similar fix, or could this be a
>> different issue?
> 
> There is no TCSR clock controller on sc8280xp, so it must be something
> else. My feeling is that this is probably triggered by the link clock
> source not being parented to the clock generated by the PHY, or PHY PLL
> isn't locked yet at that point, but I'm not sure.
> 
> I'm not able to reproduce this issue on my x13s.
> 

It only happens when mdss0_dp2 is not connected to a display during 
boot. I believe laptops usually use mdss0_dp3, and it's always connected.

I guess the Windows Dev Kit may have the same issue, since it also uses 
mdss0_dp2 as an external mini-DP port.

-- 
Best regards,
Xilin Wu <sophon at radxa.com>