[PATCH v3 1/9] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY

[Biju Das]

Hi All,

> -----Original Message-----
> From: Biju <biju.das.au at gmail.com>
> Sent: 16 September 2025 16:03
> Subject: [PATCH v3 1/9] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY
> 
> From: Biju Das <biju.das.jz at bp.renesas.com>
> 
> Document Renesas RZ/G3E USB3.0 PHY. This IP is connected between USB3HOST and PHY module. The main
> functions of the module are as follows:
>  - Reset control
>  - Control of PHY input pins
>  - Monitoring of PHY output pins
> 
> Acked-by: Conor Dooley <conor.dooley at microchip.com>
> Signed-off-by: Biju Das <biju.das.jz at bp.renesas.com>
> ---
> v2->v3:
>  * No change.
> v1->v2:
>  * Collected tag.
> ---
>  .../bindings/phy/renesas,rzg3e-usb3-phy.yaml  | 63 +++++++++++++++++++
>  1 file changed, 63 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml
> b/Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml
> new file mode 100644
> index 000000000000..b86dc7a291a4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml
> @@ -0,0 +1,63 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/renesas,rzg3e-usb3-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G3E USB 3.0 PHY
> +
> +maintainers:
> +  - Biju Das <biju.das.jz at bp.renesas.com>
> +
> +properties:
> +  compatible:
> +    const: renesas,r9a09g047-usb3-phy
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: APB bus clock
> +      - description: USB 2.0 PHY reference clock
> +      - description: USB 3.0 PHY reference clock
> +
> +  clock-names:
> +    items:
> +      - const: pclk
> +      - const: core
> +      - const: ref_alt_clk_p
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  '#phy-cells':
> +    const: 0
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - power-domains
> +  - resets
> +  - '#phy-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
> +
> +    usb-phy at 15870000 {
> +        compatible = "renesas,r9a09g047-usb3-phy";
> +        reg = <0x15870000 0x10000>;
> +        clocks = <&cpg CPG_MOD 0xb0>, <&cpg CPG_CORE 13>, <&cpg CPG_CORE 12>;
> +        clock-names = "pclk", "core", "ref_alt_clk_p";
> +        power-domains = <&cpg>;
> +        resets = <&cpg 0xaa>;
> +        #phy-cells = <0>;
> +    };
> --
> 2.43.0

Gentle ping.

Cheers,
Biju