[PATCH v3 3/4] dt-bindings: phy: google: Add Google Tensor G5 USB PHY

[Rob Herring]

On Mon, Oct 13, 2025 at 06:46:39PM -0700, Roy Luo wrote:
> On Fri, Oct 10, 2025 at 5:11 PM Krzysztof Kozlowski <krzk at kernel.org> wrote:
> >
> > On 10/10/2025 22:16, Roy Luo wrote:
> > > +  reg:
> > > +    items:
> > > +      - description: USB2 PHY configuration registers.
> > > +      - description: DisplayPort top-level registers.
> > > +      - description: USB top-level configuration registers.
> > > +
> > > +  reg-names:
> > > +    items:
> > > +      - const: u2phy_cfg
> > > +      - const: dp_top
> > > +      - const: usb_top_cfg
> > > +
> > > +  "#phy-cells":
> > > +    const: 1
> > > +
> > > +  clocks:
> > > +    maxItems: 1
> > > +
> > > +  resets:
> > > +    maxItems: 1
> > > +
> > > +  power-domains:
> > > +    maxItems: 1
> > > +
> > > +  orientation-switch:
> > > +    type: boolean
> > > +    description:
> > > +      Indicates the PHY as a handler of USB Type-C orientation changes
> > > +
> > > +required:
> > > +  - compatible
> > > +  - reg
> > > +  - reg-names
> > > +  - "#phy-cells"
> > > +  - clocks
> > > +  - resets
> > > +  - power-domains
> > > +  - orientation-switch
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > +  - |
> > > +    soc {
> > > +        #address-cells = <2>;
> > > +        #size-cells = <2>;
> > > +
> > > +        usb_phy: usb_phy at c410000 {
> > > +            compatible = "google,gs5-usb-phy";
> > > +            reg = <0 0x0c450014 0 0xc>,
> > > +                  <0 0x0c637000 0 0xa0>,
> >
> > You probably miss DP support and this does not belong here.
> 
> This register space isn't solely for DP operation, a significant portion
> manages the custom combo PHY. Consequently, this space is essential
> even for USB-only operation. We can expect more registers in the space
> to be utilized when DP support is added.
> 
> While I acknowledge the current name is confusing, it directly reflects
> the hardware documentation. We can either adhere to the hardware
> documentation's naming or propose a more descriptive alternative.
> What's your preference?
> 
> >
> > > +                  <0 0x0c45002c 0 0x4>;
> >
> > That's not a separate address space. I really, really doubt that
> > hardware engineers came with address spaces of one word long.
> 
> I initially created this space to access the usb2only mode register,
> which must be programmed when the controller operates in high-speed
> only mode without the USB3 PHY initialized. Upon review, I now
> believe the controller driver is the better location for this configuration,
> as the register logically belongs there and the controller can tell
> whether usb3 phy is going to be initialized.
> 
> That is, I'm removing this register space in the next patch.

You are missing the point. What exists from 0x0c450020-2c and 
0x0c450000-0x14 for that matter? Hardware blocks don't just start on 
unaligned boundaries like 0x14 or 0x2c. DT describes the h/w blocks, not 
just nodes of what a driver needs. So if the 0x2c register needs to be 
accessed by the USB driver, that's fine, but the register doesn't go in 
the USB controller node 'reg'. A property with a phandle to the node 
defining all the 0x0c450000 registers and an offset (if needed) is 
typically what we do there. Or you can just find that node by 
compatible.

Rob