[PATCH v3 1/4] dt-bindings: usb: dwc3: Add Google Tensor G5 DWC3

[Krzysztof Kozlowski]

On 14/10/2025 03:40, Roy Luo wrote:
> On Fri, Oct 10, 2025 at 5:09 PM Krzysztof Kozlowski <krzk at kernel.org> wrote:
>>
>> On 10/10/2025 22:16, Roy Luo wrote:
>>> Document the device tree bindings for the DWC3 USB controller found in
>>> Google Tensor SoCs, starting with the G5 generation.
>>>
>>> The Tensor G5 silicon represents a complete architectural departure from
>>> previous generations (like gs101), including entirely new clock/reset
>>> schemes, top-level wrapper and register interface. Consequently,
>>> existing Samsung/Exynos DWC3 USB bindings are incompatible, necessitating
>>> this new device tree binding.
>>>
>>> The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features
>>> Dual-Role Device single port with hibernation support.
>>
>> You still mix, completely unnecessarily, subsystems. For Greg this is
>> actually even undesired, but regardless don't do this for any cases
>> because it just makes everything slower or more difficult to apply.
>>
>> Really, think how maintainers should deal with your patches.
>>
> 
> Understood, I will separate the patches into two distinct series: one for
> the controller and one for the PHY.
> Appreciate the feedback and the explanation.
> 
>>>
>>> Signed-off-by: Roy Luo <royluo at google.com>
>>> ---
>>>  .../bindings/usb/google,gs5-dwc3.yaml         | 141 ++++++++++++++++++
>>>  1 file changed, 141 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml
>>> new file mode 100644
>>> index 000000000000..6fadea7f41e8
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/usb/google,gs5-dwc3.yaml
>>> @@ -0,0 +1,141 @@
>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>> +# Copyright (c) 2025, Google LLC
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/usb/google,gs5-dwc3.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Google Tensor Series (G5+) DWC3 USB SoC Controller
>>> +
>>> +maintainers:
>>> +  - Roy Luo <royluo at google.com>
>>> +
>>> +description:
>>> +  Describes the DWC3 USB controller block implemented on Google Tensor SoCs,
>>> +  starting with the G5 generation. Based on Synopsys DWC3 IP, the controller
>>> +  features Dual-Role Device single port with hibernation add-on.
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: google,gs5-dwc3
>>> +
>>> +  reg:
>>> +    items:
>>> +      - description: Core DWC3 IP registers.
>>> +      - description: USB host controller configuration registers.
>>> +      - description: USB custom interrrupts control registers.
>>> +
>>> +  reg-names:
>>> +    items:
>>> +      - const: dwc3_core
>>> +      - const: host_cfg
>>> +      - const: usbint_cfg
>>> +
>>> +  interrupts:
>>> +    items:
>>> +      - description: Core DWC3 interrupt.
>>> +      - description: High speed power management event for remote wakeup from hibernation.
>>> +      - description: Super speed power management event for remote wakeup from hibernation.
>>
>> Wrap at 80 (see coding style) or just shorten these.
> 
> Ack, will fix it in the next patch.
> 
>>
>>> +
>>> +  interrupt-names:
>>> +    items:
>>> +      - const: dwc_usb3
>>
>> So just "core"?
> 
> I'd prefer to stick to "dwc_usb3" as that's
> 1. more expressive by referring to the underlying IP name,


But that's completely redundant name.

> 2. consistent with established dwc3 bindings such as
>     Documentation/devicetree/bindings/usb/snps,dwc3.yaml,

If you use only one interrupt. You don't use one interrupt here.

>     Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml,
> unless you have a strong preference for the alternative naming.

Such namings are discouraged, because they tell absolutely nothing.
Also, schematics or datasheets usually do not use them, either.


Best regards,
Krzysztof