(subset) [PATCH v3 0/4] PCI: qcom: Add support for Glymur PCIe Gen5x4

[Vinod Koul]

On Mon, 25 Aug 2025 23:01:46 -0700, Wenbin Yao wrote:
> Glymur is the next generation compute SoC of Qualcomm. This patch series
> aims to add support for the fifth PCIe instance on it. The fifth PCIe
> instance on Glymur has a Gen5 4-lane PHY. Patch [1/4] documents PHY as a
> separate compatible and Patch [2/4] documents controller as a separate
> compatible. Patch [3/4] describles the new PCS offsets in a dedicated
> header file. Patch [4/4] adds configuration and compatible for PHY.
> 
> [...]

Applied, thanks!

[1/4] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the Glymur QMP PCIe PHY
      commit: d877f881cec508a46f76dbed7c46ab78bc1c0d87
[3/4] phy: qcom-qmp: pcs: Add v8.50 register offsets
      commit: bc2ba6e3fb8a35cd83813be1bd4c5f066a401d8b
[4/4] phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen5x4 PHY
      commit: 1797c6677ad6298ca463b6ee42245e19e9cc1206

Best regards,
-- 
~Vinod