[PATCH v2 1/2] phy: qcom: qmp-pcie: Update PHY settings for SA8775P

[Konrad Dybcio]

On 5/19/25 2:25 PM, Mrinmay Sarkar wrote:
> On Sat, May 17, 2025 at 11:46 PM Konrad Dybcio <
> konrad.dybcio at oss.qualcomm.com> wrote:
>>
>> On 5/14/25 1:37 PM, Mrinmay Sarkar wrote:
>>> From: Mrinmay Sarkar <mrinmay.sarkar at oss.qualcomm.com>
>>>
>>> Make changes to update the PHY settings to align with the latest
>>> PCIe PHY Hardware Programming Guide for both PCIe controllers
>>> on the SA8775P platform.
>>>
>>> Add the ln_shrd region for SA8775P, incorporating new register
>>> writes as specified in the updated Hardware Programming Guide.
>>>
>>> Update pcs table for QCS8300, since both QCS8300 and SA8775P are
>>> closely related and share same pcs settings.
>>>
>>> Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar at oss.qualcomm.com>
>>> ---
>>
>> So I took a closer look and please re-validate the changes, I
>> checked one write randomly and it turned out to be inconsistent
>>
>> [...]
>>
>>
>>> -     QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),
>>> -     QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
>>> +     QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x03),
>>
>> ^ this should be 0x0a according to reference v1.19 for RC mode
>>
> As per v1.19 for SA8775 RC mode I can see the value for this is 0x03 only.

Ah right, the docs are structured in a confusing way..

Konrad