[PATCH v2 2/2] arm64: dts: qcom: sa8775p: Remove max link speed property for PCIe EP

[neil.armstrong at linaro.org]

On 14/05/2025 13:37, Mrinmay Sarkar wrote:
> From: Mrinmay Sarkar <mrinmay.sarkar at oss.qualcomm.com>
> 
> The maximum link speed was previously restricted to Gen3 due to the
> absence of Gen4 equalization support in the driver.
> 
> Add change to remove max link speed property, Since Gen4 equalization
> support has already been added into the driver.

Which driver, PHY or Controller ? does this change depends on the patch 1 PHY settings update ?

> 
> Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar at oss.qualcomm.com>
> ---
>   arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 --
>   1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 5bd0c03476b143444543c68cd1c1d475c3302555..b001e9a30e863d8964219c8bd61bc328be71b256 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -6462,7 +6462,6 @@ pcie0_ep: pcie-ep at 1c00000 {
>   		power-domains = <&gcc PCIE_0_GDSC>;
>   		phys = <&pcie0_phy>;
>   		phy-names = "pciephy";
> -		max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
>   		num-lanes = <2>;
>   		linux,pci-domain = <0>;
>   
> @@ -6620,7 +6619,6 @@ pcie1_ep: pcie-ep at 1c10000 {
>   		power-domains = <&gcc PCIE_1_GDSC>;
>   		phys = <&pcie1_phy>;
>   		phy-names = "pciephy";
> -		max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
>   		num-lanes = <4>;
>   		linux,pci-domain = <1>;
>   
>