[PATCH v3 5/6] arm64: dts: qcom: ipq5018: Add PCIe related nodes
George Moussalem
george.moussalem at outlook.com
Wed Mar 12 23:09:09 PDT 2025
On 3/8/25 19:08, Konrad Dybcio wrote:
> On 5.03.2025 2:41 PM, George Moussalem wrote:
>> From: Sricharan Ramabadhran <quic_srichara at quicinc.com>
>>
>> From: Nitheesh Sekar <quic_nsekar at quicinc.com>
>>
>> Add phy and controller nodes for a 2-lane Gen2 and
>> a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
>> one global interrupt.
>>
>> Signed-off-by: Nitheesh Sekar <quic_nsekar at quicinc.com>
>> Signed-off-by: Sricharan R <quic_srichara at quicinc.com>
>> Signed-off-by: George Moussalem <george.moussalem at outlook.com>
>> ---
>
> [...]
>
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 0x7>;
>> + interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
>> + <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
>> + <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
>> + <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
>
> Please all the comments in this patch, they're not very useful
Will remove in next version, thanks!
>
> Konrad
Best regards,
George
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