[PATCH v7 3/4] phy: rockchip-pcie: Enable all four lanes if required

[Geraldo Nascimento]

On Mon, Jun 30, 2025 at 02:48:25PM +0100, Robin Murphy wrote:
> On 29/06/2025 9:58 pm, Geraldo Nascimento wrote:
> > Current code enables only Lane 0 because pwr_cnt will be incremented on
> > first call to the function. Let's reorder the enablement code to enable
> > all 4 lanes through GRF.
> 
> As usual the TRM isn't very clear, but the way it describes the 
> GRF_SOC_CON_5_PCIE bits does suggest they're driving external input 
> signals of the phy block, so it seems reasonable that it could be OK to 
> update the register itself without worrying about releasing the phy from 
> reset first. In that case I'd agree this seems the cleanest fix, and if 
> it works empirically then I think I'm now sufficiently convinced too;
> 
> Reviewed-by: Robin Murphy <robin.murphy at arm.com>

Hi Robin and Neil,

Thank you both for the positive reviews and the effort.

I must admit however that it looks like this patch was lifted verbatim
from Armbian and I'm missing the Signed-off-by from the original author.

As Robin may attest, I initially started by blindingly enabling all
lanes which, of course, is no good. I tried a suggestion by Robin which
did not work, and eventually settled on this Armbian solution, which at
least has got some battle-testing.

I already contacted Valmintas Paliksa, the original author of the patch,
and asked permission to use his Signed-off-by. I'm aware I could probably
use the Signed-off-by without strict permission, but it does not feel
right to me.

Thanks,
Geraldo Nascimento