[PATCH] phy: qcom: phy-qcom-m31: Update IPQ5332 M31 USB phy initialization sequence
Kathiravan Thirumoorthy
kathiravan.thirumoorthy at oss.qualcomm.com
Wed Jun 25 21:13:46 PDT 2025
On 6/25/2025 7:28 PM, Konrad Dybcio wrote:
> On 6/25/25 9:00 AM, Kathiravan Thirumoorthy wrote:
>> The current configuration used for the IPQ5332 M31 USB PHY fails the
>> Near End High Speed Signal Quality compliance test. To resolve this,
>> update the initialization sequence as specified in the Hardware Design
>> Document.
>>
>> Fixes: 08e49af50701 ("phy: qcom: Introduce M31 USB PHY driver")
>> Cc: stable at kernel.org
>> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy at oss.qualcomm.com>
>> ---
>> drivers/phy/qualcomm/phy-qcom-m31.c | 14 ++++++++++----
>> 1 file changed, 10 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-m31.c b/drivers/phy/qualcomm/phy-qcom-m31.c
>> index 7caeea1b109e922c0cd12e985bc8868d5bce8b4f..1a8a0f1262cd95bc00dfbf7397a1c48d88d52327 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-m31.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-m31.c
>> @@ -58,12 +58,14 @@
>> #define USB2_0_TX_ENABLE BIT(2)
>>
>> #define USB2PHY_USB_PHY_M31_XCFGI_4 0xc8
>> - #define HSTX_SLEW_RATE_565PS GENMASK(1, 0)
>> + #define HSTX_SLEW_RATE_400PS GENMASK(2, 0)
>> #define PLL_CHARGING_PUMP_CURRENT_35UA GENMASK(4, 3)
>> #define ODT_VALUE_38_02_OHM GENMASK(7, 6)
>>
>> +#define USB2PHY_USB_PHY_M31_XCFGI_9 0xDC
> lowercase hex, please
>
> also, please add it below XCFGI_5, so that it's sorted
> both by name and by address
Ack. Will address this in V2.
>
> FWIW I can't find anything that would back up these changes, but
> I trust what you're saying is true
Thank You!. These changes are tested and confirmed by the relevant
folks. I will try to find the doc and share it offline for reference.
>
> Konrad
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