[PATCH v4 3/3] arm64: dts: qcom: sa8775p: Add PCIe lane equalization preset properties

[Ziyue Zhang]

Add PCIe lane equalization preset properties with all values set to 5 for
8.0 GT/s and 16.0 GT/s data rates to enhance link stability.

Co-developed-by: Qiang Yu <qiang.yu at oss.qualcomm.com>
Signed-off-by: Qiang Yu <qiang.yu at oss.qualcomm.com>
Signed-off-by: Ziyue Zhang <ziyue.zhang at oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio at oss.qualcomm.com>
Acked-by: Manivannan Sadhasivam <mani at kernel.org>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index fed34717460f..61f094c51815 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -7642,6 +7642,9 @@ pcie0: pcie at 1c00000 {
 		phys = <&pcie0_phy>;
 		phy-names = "pciephy";
 
+		eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
+		eq-presets-16gts = /bits/ 8 <0x55 0x55>;
+
 		status = "disabled";
 
 		pcieport0: pcie at 0 {
@@ -7808,6 +7811,9 @@ pcie1: pcie at 1c10000 {
 		phys = <&pcie1_phy>;
 		phy-names = "pciephy";
 
+		eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
+		eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
+
 		status = "disabled";
 
 		pcie at 0 {
-- 
2.34.1