[PATCH v4 1/2] phy: cadence: cdns-dphy: Fix PLL lock and O_CMN_READY polling
Devarsh Thakkar
devarsht at ti.com
Thu Jul 10 04:35:57 PDT 2025
Hello,
On 05/07/25 08:32, kernel test robot wrote:
> Hi Devarsh,
>
> kernel test robot noticed the following build errors:
>
> [auto build test ERROR on linus/master]
> [also build test ERROR on v6.16-rc4 next-20250704]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
> url: https://github.com/intel-lab-lkp/linux/commits/Devarsh-Thakkar/phy-cadence-cdns-dphy-Fix-PLL-lock-and-O_CMN_READY-polling/20250704-210349
> base: linus/master
> patch link: https://lore.kernel.org/r/20250704125915.1224738-2-devarsht%40ti.com
> patch subject: [PATCH v4 1/2] phy: cadence: cdns-dphy: Fix PLL lock and O_CMN_READY polling
> config: x86_64-buildonly-randconfig-003-20250705 (https://download.01.org/0day-ci/archive/20250705/202507051038.XCl5miJ7-lkp@intel.com/config)
> compiler: clang version 20.1.7 (https://github.com/llvm/llvm-project 6146a88f60492b520a36f8f8f3231e15f3cc6082)
> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250705/202507051038.XCl5miJ7-lkp@intel.com/reproduce)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp at intel.com>
> | Closes: https://lore.kernel.org/oe-kbuild-all/202507051038.XCl5miJ7-lkp@intel.com/
>
> All errors (new ones prefixed by >>):
>
>>> drivers/phy/cadence/cdns-dphy.c:408:45: error: no member named 'hs_clk_rate' in 'struct cdns_dphy_cfg'
> 408 | ret = cdns_dphy_tx_get_band_ctrl(dphy->cfg.hs_clk_rate);
> | ~~~~~~~~~ ^
> 1 error generated.
>
This is expected, since as mentioned in cover-letter this patch needs to
be applied on top of [1] and [2] from the series [3] as suggested in the
review [4] for the previous revision.
[1]:
https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-4-862c841dbe02@ideasonboard.com/
[2]:
https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-5-862c841dbe02@ideasonboard.com/
[3]:
https://lore.kernel.org/all/20250618-cdns-dsi-impro-v4-0-862c841dbe02@ideasonboard.com/
[4]:
https://lore.kernel.org/all/218ba1a0-068d-4bb2-bba2-2739afa7f470@ideasonboard.com/
Regards
Devarsh
>
> vim +408 drivers/phy/cadence/cdns-dphy.c
>
> 370
> 371 static int cdns_dphy_power_on(struct phy *phy)
> 372 {
> 373 struct cdns_dphy *dphy = phy_get_drvdata(phy);
> 374 int ret;
> 375 u32 reg;
> 376
> 377 if (!dphy->is_configured || dphy->is_powered)
> 378 return -EINVAL;
> 379
> 380 clk_prepare_enable(dphy->psm_clk);
> 381 clk_prepare_enable(dphy->pll_ref_clk);
> 382
> 383 /*
> 384 * Configure the internal PSM clk divider so that the DPHY has a
> 385 * 1MHz clk (or something close).
> 386 */
> 387 ret = cdns_dphy_setup_psm(dphy);
> 388 if (ret) {
> 389 dev_err(&dphy->phy->dev, "Failed to setup PSM with error %d\n", ret);
> 390 goto err_power_on;
> 391 }
> 392
> 393 /*
> 394 * Configure attach clk lanes to data lanes: the DPHY has 2 clk lanes
> 395 * and 8 data lanes, each clk lane can be attache different set of
> 396 * data lanes. The 2 groups are named 'left' and 'right', so here we
> 397 * just say that we want the 'left' clk lane to drive the 'left' data
> 398 * lanes.
> 399 */
> 400 cdns_dphy_set_clk_lane_cfg(dphy, DPHY_CLK_CFG_LEFT_DRIVES_LEFT);
> 401
> 402 /*
> 403 * Configure the DPHY PLL that will be used to generate the TX byte
> 404 * clk.
> 405 */
> 406 cdns_dphy_set_pll_cfg(dphy, &dphy->cfg);
> 407
> > 408 ret = cdns_dphy_tx_get_band_ctrl(dphy->cfg.hs_clk_rate);
> 409 if (ret < 0) {
> 410 dev_err(&dphy->phy->dev, "Failed to get band control value with error %d\n", ret);
> 411 goto err_power_on;
> 412 }
> 413
> 414 reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, ret) |
> 415 FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, ret);
> 416 writel(reg, dphy->regs + DPHY_BAND_CFG);
> 417
> 418 /* Start TX state machine. */
> 419 writel(DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN,
> 420 dphy->regs + DPHY_CMN_SSM);
> 421
> 422 ret = cdns_dphy_wait_for_pll_lock(dphy);
> 423 if (ret) {
> 424 dev_err(&dphy->phy->dev, "Failed to lock PLL with error %d\n", ret);
> 425 goto err_power_on;
> 426 }
> 427
> 428 ret = cdns_dphy_wait_for_cmn_ready(dphy);
> 429 if (ret) {
> 430 dev_err(&dphy->phy->dev, "O_CMN_READY signal failed to assert with error %d\n",
> 431 ret);
> 432 goto err_power_on;
> 433 }
> 434
> 435 dphy->is_powered = true;
> 436
> 437 return 0;
> 438
> 439 err_power_on:
> 440 clk_disable_unprepare(dphy->pll_ref_clk);
> 441 clk_disable_unprepare(dphy->psm_clk);
> 442
> 443 return ret;
> 444 }
> 445
>
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