[PATCH 2/2] phy: qcom: qmp-pcie: Add PHY register retention support

[Dmitry Baryshkov]

On Tue, 21 Jan 2025 at 11:43, Wenbin Yao <quic_wenbyao at quicinc.com> wrote:
>
> From: Qiang Yu <quic_qianyu at quicinc.com>
>
> Currently, BCR reset and PHY register setting are mandatory for every port
> before link training. However, some QCOM PCIe PHYs support no_csr reset.
> Different than BCR reset that is used to reset entire PHY including
> hardware and register, once no_csr reset is toggled, only PHY hardware will
> be reset but PHY registers will be retained,

I'm sorry, I can't parse this.

> which means PHY setting can
> be skipped during PHY init if PCIe link was enabled in booltloader and only
> no_csr is toggled after that.
>
> Hence, determine whether the PHY has been enabled in bootloader by
> verifying QPHY_START_CTRL register. If it is programmed and no_csr reset is
> present, skip BCR reset and PHY register setting, so that PCIe link can be
> established with no_csr reset only.

This doesn't tell us why we want to do so. The general rule is not to
depend on the bootloaders at all. The reason is pretty simple: it is
hard to update bootloaders, while it is relatively easy to update the
kernel. If the hardware team issues any kind of changes to the
programming tables, the kernel will get them earlier than the
bootloader.

>
> Signed-off-by: Qiang Yu <quic_qianyu at quicinc.com>
> Signed-off-by: Wenbin Yao <quic_wenbyao at quicinc.com>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 91 +++++++++++++++---------
>  1 file changed, 58 insertions(+), 33 deletions(-)
>
-- 
With best wishes
Dmitry