[PATCH v7 6/7] arm64: dts: qcom: ipq5332: Add PCIe related nodes
Manivannan Sadhasivam
manivannan.sadhasivam at linaro.org
Mon Feb 3 08:26:17 PST 2025
On Wed, Jan 22, 2025 at 12:04:10PM +0530, Varadarajan Narayanan wrote:
> From: Praveenkumar I <quic_ipkumar at quicinc.com>
>
> Add phy and controller nodes for pcie0_x1 and pcie1_x2.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio at oss.qualcomm.com>
> Signed-off-by: Praveenkumar I <quic_ipkumar at quicinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada at quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org>
One minor comment below.
[...]
> + assigned-clocks = <&gcc GCC_PCIE3X2_AUX_CLK>,
> + <&gcc GCC_PCIE3X2_AXI_M_CLK>,
> + <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
> + <&gcc GCC_PCIE3X2_AXI_S_CLK>,
> + <&gcc GCC_PCIE3X2_RCHG_CLK>;
> +
> + assigned-clock-rates = <2000000>,
> + <266666666>,
> + <240000000>,
> + <240000000>,
> + <100000000>;
> +
Does the drivers really need to set clock rate for these many clocks?
No, as per the reply to my similar question to IPQ5424:
https://lore.kernel.org/linux-arm-msm/9206e44c-da4f-4bdb-850f-fac511f4ddc7@quicinc.com/
- Mani
--
மணிவண்ணன் சதாசிவம்
More information about the linux-phy
mailing list