[PATCH v2 2/2] phy: cadence: cdns-dphy: Update calibration wait time for startup state machine

[Tomi Valkeinen]

Hi,

On 26/03/2025 17:23, Devarsh Thakkar wrote:
> Use system characterized reset value specified in TRM [1] to program
> calibration wait time which defines number of cycles to wait for after
> startup state machine is in bandgap enable state.
> 
> This fixes PLL lock timeout error faced while using RPi DSI Panel on TI's
> AM62L and J721E SoC [2].
> 
> [1] AM62P TRM (Section ):
> https://www.ti.com/lit/pdf/spruj83
> 
> [2]:
> Link: https://gist.github.com/devarsht/89e4830e886774fcd50aa6e29cce3a79
> 
> Cc: stable at vger.kernel.org
> Fixes: 7a343c8bf4b5 ("phy: Add Cadence D-PHY support")
> Signed-off-by: Devarsh Thakkar <devarsht at ti.com>
> ---
> V2: Introduced this as as separate patch
> 
>   drivers/phy/cadence/cdns-dphy.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c
> index c4de9e4d3e93..11fbffe5aafd 100644
> --- a/drivers/phy/cadence/cdns-dphy.c
> +++ b/drivers/phy/cadence/cdns-dphy.c
> @@ -30,6 +30,7 @@
>   
>   #define DPHY_CMN_SSM			DPHY_PMA_CMN(0x20)
>   #define DPHY_CMN_SSM_EN			BIT(0)
> +#define DPHY_CMN_SSM_CAL_WAIT_TIME	GENMASK(8, 1)
>   #define DPHY_CMN_TX_MODE_EN		BIT(9)
>   
>   #define DPHY_CMN_PWM			DPHY_PMA_CMN(0x40)
> @@ -405,6 +406,8 @@ static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
>   	reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) |
>   	      FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl);
>   	writel(reg, dphy->regs + DPHY_BAND_CFG);
> +	writel(FIELD_PREP(DPHY_CMN_SSM_CAL_WAIT_TIME, 0x14) | DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN,
> +	       dphy->regs + DPHY_CMN_SSM);

This sounds like a TI specific characterized value, but the function 
here is a generic one. Also, is the value same for all TI SoCs? Or is it 
per-soc?

  Tomi