[PATCH v2 02/15] soc: renesas: Add SYSC driver for Renesas RZ family

[Biju Das]

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert at linux-m68k.org>
> Sent: 26 November 2024 13:42
> Subject: Re: [PATCH v2 02/15] soc: renesas: Add SYSC driver for Renesas RZ family
> 
> Hi Biju,
> 
> On Tue, Nov 26, 2024 at 10:28 AM Biju Das <biju.das.jz at bp.renesas.com> wrote:
> > > -----Original Message-----
> > > From: Claudiu <claudiu.beznea at tuxon.dev>
> > > Sent: 26 November 2024 09:21
> > > Subject: [PATCH v2 02/15] soc: renesas: Add SYSC driver for Renesas
> > > RZ family
> > >
> > > From: Claudiu Beznea <claudiu.beznea.uj at bp.renesas.com>
> > >
> > > The RZ/G3S system controller (SYSC) has various registers that
> > > control signals specific to individual IPs. IP drivers must control these signals at different
> configuration phases.
> > >
> > > Add SYSC driver that allows individual SYSC consumers to control
> > > these signals. The SYSC driver exports a syscon regmap enabling IP
> > > drivers to use a specific SYSC offset and mask from the device tree, which can then be accessed
> through regmap_update_bits().
> > >
> > > Currently, the SYSC driver provides control to the USB PWRRDY signal, which is routed to the USB
> PHY.
> > > This signal needs to be managed before or after powering the USB PHY off or on.
> > >
> > > Other SYSC signals candidates (as exposed in the the hardware manual of the RZ/G3S SoC) include:
> > >
> > > * PCIe:
> > > - ALLOW_ENTER_L1 signal controlled through the SYS_PCIE_CFG register
> > > - PCIE_RST_RSM_B signal controlled through the SYS_PCIE_RST_RSM_B
> > >   register
> > > - MODE_RXTERMINATION signal controlled through SYS_PCIE_PHY register
> > >
> > > * SPI:
> > > - SEL_SPI_OCTA signal controlled through SYS_IPCONT_SEL_SPI_OCTA
> > >   register
> > >
> > > * I2C/I3C:
> > > - af_bypass I2C signals controlled through SYS_I2Cx_CFG registers
> > >   (x=0..3)
> > > - af_bypass I3C signal controlled through SYS_I3C_CFG register
> > >
> > > * Ethernet:
> > > - FEC_GIGA_ENABLE Ethernet signals controlled through SYS_GETHx_CFG
> > >   registers (x=0..1)
> > >
> > > As different Renesas RZ SoC shares most of the SYSC functionalities
> > > available on the RZ/G3S SoC, the driver if formed of a SYSC core
> > > part and a SoC specific part allowing individual SYSC SoC to provide functionalities to the SYSC
> core.
> > >
> > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj at bp.renesas.com>
> >
> > Reviewed-by: Biju Das <biju.das.jz at bp.renesas.com>
> 
> Thanks for your review!
> 
> > > ---
> > >
> > > Change in v2:
> > > - this was patch 04/16 in v1
> > > - dropped the initial approach proposed in v1 where a with a reset
> > >   controller driver was proposed to handle the USB PWRRDY signal
> > > - implemented it with syscon regmap and the SYSC signal concept
> > >   (introduced in this patch)
> 
> [...]
> 
> When reviewing, please trim your response, so other people don't have to scroll through hundreds of
> lines of quoted text, to find any other comments (if any).

Sorry for that. Will take care next time.

Cheers,
Biju