[PATCH v1 3/4] arm64: dts: qcom: qcs615: add UFS node

[Manivannan Sadhasivam]

On Wed, Nov 13, 2024 at 05:19:49PM +0800, Xin Liu wrote:
> 
> 
> 在 2024/10/26 3:24, Konrad Dybcio 写道:
> > On 17.10.2024 6:22 AM, Xin Liu wrote:
> > > From: Sayali Lokhande <quic_sayalil at quicinc.com>	
> > > 	
> > > Add the UFS Host Controller node and its PHY for QCS615 SoC.
> > > 
> > > Signed-off-by: Sayali Lokhande <quic_sayalil at quicinc.com>
> > > Co-developed-by: Xin Liu <quic_liuxin at quicinc.com>
> > > Signed-off-by: Xin Liu <quic_liuxin at quicinc.com>
> > > ---
> > 
> > + Taniya (see below)
> > 
> > >   arch/arm64/boot/dts/qcom/qcs615.dtsi | 74 ++++++++++++++++++++++++++++
> > >   1 file changed, 74 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > > index fcba83fca7cf..689418466dc2 100644
> > > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > > @@ -458,6 +458,80 @@ mmss_noc: interconnect at 1740000 {
> > >   			qcom,bcm-voters = <&apps_bcm_voter>;
> > >   		};
> > > +		ufs_mem_hc: ufs at 1d84000 {
> > 
> > ufshc@ would be consistent with other files in dts/qcom
> > 
> I referred to qcom files such as sa8775p/sm8550/sm8650 etc.All use ufs@

That's an oddity. But 'ufshc' is documented in the devicetree spec. So you
should use it for UFSHC nodes.

- Mani

> > 
> > > +			compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
> > > +			reg = <0x0 0x01d84000 0x0 0x3000>, <0x0 0x01d90000 0x0 0x8000>;
> > > +			reg-names = "std", "ice";
> > 
> > One per line, please
> Thank you, I will fix it next version.
> > 
> > > +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> > > +			phys = <&ufs_mem_phy>;
> > > +			phy-names = "ufsphy";
> > > +			lanes-per-direction = <1>;
> > > +			#reset-cells = <1>;
> > > +			resets = <&gcc GCC_UFS_PHY_BCR>;
> > > +			reset-names = "rst";
> > > +
> > > +			power-domains = <&gcc UFS_PHY_GDSC>;
> > > +			required-opps = <&rpmhpd_opp_nom>;
> > > +
> > > +			iommus = <&apps_smmu 0x300 0x0>;
> > > +			dma-coherent;
> > > +
> > > +			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
> > > +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> > > +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> > > +					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
> > > +			interconnect-names = "ufs-ddr",
> > > +					     "cpu-ufs";
> > > +
> > > +			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> > > +				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> > > +				 <&gcc GCC_UFS_PHY_AHB_CLK>,
> > > +				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> > > +				 <&rpmhcc RPMH_CXO_CLK>,
> > > +				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> > > +				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> > > +				 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
> > > +			clock-names = "core_clk",
> > > +				      "bus_aggr_clk",
> > > +				      "iface_clk",
> > > +				      "core_clk_unipro",
> > > +				      "ref_clk",
> > > +				      "tx_lane0_sync_clk",
> > > +				      "rx_lane0_sync_clk",
> > > +				      "ice_core_clk";
> > > +			freq-table-hz = <50000000 200000000>,
> > > +					<0 0>,
> > > +					<0 0>,
> > > +					<37500000 150000000>,
> > > +					<0 0>,
> > > +					<0 0>,
> > > +					<0 0>,
> > > +					<75000000 300000000>;
> > 
> > Please try to match the order of properties present in sm8650.dtsi
> Thank you, I will fix it next version.
> > 
> > And please use an OPP table instead of freq-table-hz (see sm8*5*50.dtsi)
> Thank you, I will fix it next version.
> > 
> > > +
> > > +			status = "disabled";
> > > +		};
> > > +
> > > +		ufs_mem_phy: phy at 1d87000 {
> > > +			compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy";
> > > +			reg = <0x0 0x01d87000 0x0 0xe00>;
> > 
> > This register region is a bit longer
> I just confirmed again, there's no problem here.
> > 
> > > +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> > > +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> > > +				 <&gcc GCC_UFS_MEM_CLKREF_CLK>;
> > > +			clock-names = "ref",
> > > +				      "ref_aux",
> > > +				      "qref";
> > > +
> > > +			power-domains = <&gcc UFS_PHY_GDSC>;
> > > +
> > > +			resets = <&ufs_mem_hc 0>;
> > > +			reset-names = "ufsphy";
> > > +
> > > +			#clock-cells = <1>;
> > 
> > The PHY is a clock provider. Normally, it's a parent of
> > gcc_ufs_phy_[rt]x_symbol_n clocks.
> > 
> > Taniya, could you please wire that up in your patchset?
> > 
> > Konrad
> 

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