[PATCH v2 1/2] Add write DP phyd register from parse dts

[AngeloGioacchino Del Regno]

Il 10/05/24 13:04, Liankun Yang ha scritto:
> During the testing phase, screen flickering is observed when
> using displayport for screen casting. Relevant SSC register parameters
> are set in dts to address the screen flickering issue effectively and
> improve compatibility with different devices by adjusting the SSC gear.
> 
> Obtaining the DPTX node, parsing the dts to obtain PHY register address
> and value can adapt to settings of different manufacturers projects.
> 
> Changeds in v2:
> - Optimized method of writing to DP PHY register
> https://patchwork.kernel.org/project/linux-mediatek/patch/
> 20240403040517.3279-1-liankun.yang at mediatek.com/
> 
> Signed-off-by: Liankun Yang <liankun.yang at mediatek.com>

There's no devicetree support in this driver - infact, it's being probed by
mtk-dp as a platform device.

You keep sending untested stuff. Fourth time in a row.

Please, TEST YOUR COMMITS upstream before sending!

Regards,
Angelo

> ---
>   drivers/phy/mediatek/phy-mtk-dp.c | 37 +++++++++++++++++++++++++++++++
>   1 file changed, 37 insertions(+)
> 
> diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c
> index d7024a144335..ce78112d5938 100644
> --- a/drivers/phy/mediatek/phy-mtk-dp.c
> +++ b/drivers/phy/mediatek/phy-mtk-dp.c
> @@ -28,6 +28,10 @@
>   #define MTK_DP_PHY_DIG_SW_RST		(PHY_OFFSET + 0x38)
>   #define DP_GLB_SW_RST_PHYD		BIT(0)
>   
> +#define MTK_DP_PHY_DIG_GLB_DA_REG_14	(PHY_OFFSET + 0xD8)
> +#define XTP_GLB_TXPLL_SSC_DELTA_RBR_DEFAULT	GENMASK(15, 0)
> +#define XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULT	GENMASK(31, 16)
> +
>   #define MTK_DP_LANE0_DRIVING_PARAM_3		(PHY_OFFSET + 0x138)
>   #define MTK_DP_LANE1_DRIVING_PARAM_3		(PHY_OFFSET + 0x238)
>   #define MTK_DP_LANE2_DRIVING_PARAM_3		(PHY_OFFSET + 0x338)
> @@ -78,10 +82,39 @@
>   #define DRIVING_PARAM_8_DEFAULT	(XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
>   				 XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
>   
> +#define SSC_SETTING	"dp-ssc-setting"
> +#define RG_XTP_GLB_TXPLL_SSC_DELTA_HBR	"ssc-delta-hbr"
> +
>   struct mtk_dp_phy {
>   	struct regmap *regs;
> +	struct device *dev;
>   };
>   
> +static int mtk_dp_set_ssc_config(struct phy *phy, struct mtk_dp_phy *dp_phy)
> +{
> +	int ret;
> +	u32 read_value = 0, reg_mask = 0;
> +	struct device_node *ssc_node = NULL;
> +
> +	ssc_node = of_find_node_by_name(dp_phy->dev->of_node, SSC_SETTING);
> +	if (!ssc_node) {
> +		dev_err(&phy->dev, "SSC node is NULL\n");
> +		return -ENODEV;
> +	}
> +
> +	ret = of_property_read_u32(ssc_node, RG_XTP_GLB_TXPLL_SSC_DELTA_HBR, &read_value);
> +	if (ret < 0 || !read_value) {
> +		dev_err(&phy->dev, "Read SSC vlaue fail!\n");
> +		return -EINVAL;
> +	}
> +	read_value |= read_value << 16;
> +	reg_mask |= XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULT;
> +
> +	regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_GLB_DA_REG_14, reg_mask, read_value);
> +
> +	return 0;
> +}
> +
>   static int mtk_dp_phy_init(struct phy *phy)
>   {
>   	struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
> @@ -137,6 +170,8 @@ static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
>   	regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1,
>   			   TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0);
>   
> +	mtk_dp_set_ssc_config(phy, dp_phy);
> +
>   	return 0;
>   }
>   
> @@ -186,6 +221,8 @@ static int mtk_dp_phy_probe(struct platform_device *pdev)
>   	if (!dev->of_node)
>   		phy_create_lookup(phy, "dp", dev_name(dev));
>   
> +	dp_phy->dev = dev;
> +
>   	return 0;
>   }
>