[PATCH] phy: lynx-28g: use read_poll_timeout when waiting for halt/reset bits

[Josua Mayer]

Am 18.02.24 um 15:09 schrieb Josua Mayer:

> Power-on and -off functions set and wait for self-clearing reset-
> and halt-bits in serdes registers.
> In certain operating conditions these bits may not actually clear.
>
> Replace the infinite while-loops with read_poll_timeout to ensure that
> power_on and power_off will always return even when the bits did not
> clear within a full second.
>
> On timeout print an error message and return error code.
> In this situation the serdes lane has an invalid state,
> without no known recovery procedure.
>
> This fixes an infinite loop / hang during boot observed on a
> misconfigured lx2160a system where serdes #1 PLLS (161MHz) and PLLF
> (100MHz) were mistakenly swapped.
> After reset the PLL's did lock (to wrong rates) but the serdes locked up
> and never cleared either lane-specific or global halt- and reset-bits.
>
> Signed-off-by: Josua Mayer <josua at solid-run.com>
> ---
>   drivers/phy/freescale/phy-fsl-lynx-28g.c | 42 ++++++++++++++++++++++++--------
>   1 file changed, 32 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
> index e2187767ce00..5ae5b47619f8 100644
> --- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
> +++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
> @@ -335,6 +335,7 @@ static int lynx_28g_power_off(struct phy *phy)
> ...
> +	err = read_poll_timeout(lynx_28g_lane_read, rrstctl,
> +				!(rrstctl & LYNX_28G_LNaRRSTCTL_HLT_REQ),
> +				10000, 1000000, false, lane, LNaRRSTCTL);
> +	if (err) {
> +		dev_err(&phy->dev, "tx lane halt failed: %d\n", err);
Message should be "rx" lane, will fix in v2.