[PATCH v3 2/5] phy: qcom: Introduce PCIe UNIPHY 28LP driver

[Vinod Koul]

On 17-12-24, 15:33, Varadarajan Narayanan wrote:

> +#define RST_ASSERT_DELAY_MIN_US		100
> +#define RST_ASSERT_DELAY_MAX_US		150
> +#define PIPE_CLK_DELAY_MIN_US		5000
> +#define PIPE_CLK_DELAY_MAX_US		5100
> +#define CLK_EN_DELAY_MIN_US		30
> +#define CLK_EN_DELAY_MAX_US		50
> +#define CDR_CTRL_REG_1		0x80
> +#define CDR_CTRL_REG_2		0x84
> +#define CDR_CTRL_REG_3		0x88
> +#define CDR_CTRL_REG_4		0x8C

Lower case here and other places and please be consistent

> +static inline int phy_pipe_clk_register(struct qcom_uniphy_pcie  *phy,
> +					struct device_node *np)
> +{
> +	const struct qcom_uniphy_pcie_data *data = phy->data;
> +	struct clk_hw *hw;
> +	char name[64];
> +	int ret;
> +
> +	snprintf(name, sizeof(name), "%s_pipe_clk_src", np->name);
> +	hw = devm_clk_hw_register_fixed_rate(phy->dev, name, NULL, 0,
> +					     data->pipe_clk_rate);
> +	if (IS_ERR(hw))
> +		return dev_err_probe(phy->dev, PTR_ERR(hw),
> +				     "Unable to register %s\n", name);
> +
> +	ret = devm_of_clk_add_hw_provider(phy->dev, of_clk_hw_simple_get, hw);
> +	if (ret)
> +		return ret;
> +
> +	return 0;

just return devm_of_clk_add_hw_provider()

-- 
~Vinod